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公开(公告)号：US20180260508A1
公开(公告)日：2018-09-13
申请号：US15979194
申请日：2018-05-14
申请人： Synopsys, Inc.
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5027
摘要： A hardware verification system according to one embodiment includes, in part, a plurality of programmable devices. The plurality of programmable devices include a master scheduler, a plurality of schedulers and a plurality of programmable delay elements. A first one of the plurality of schedulers is configured to receive one or more delay values associated with one or more of the plurality of delay elements. Each of the plurality of programmable delay elements corresponds to a delay. The first scheduler is further configured to send a parameter corresponding to the one or more delay values to the master scheduler, and generate one or more signals corresponding to the one or more delay elements in response to a control signal the first scheduler receives from the master scheduler.
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公开(公告)号：US20170337310A1
公开(公告)日：2017-11-23
申请号：US15670962
申请日：2017-08-07
申请人： Synopsys, Inc.
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F17/5081
摘要： Embodiments relate to the emulation of circuits, and representation of unknown states of signals. A disclosed system (and method and computer program product) includes an emulation environment to convert a digital signal of a DUT in a form capable of representing an unknown state. In addition, the disclosed system converts digital logic circuits such as Boolean logic, flip flops, latches, and memory circuits to be operable with signals having unknown states. Thus, an unknown state of a signal is indicated and propagated through digital logic circuits represented in a disclosed semantic to enable prompt detection of improper operation of the DUT, for example, due to power shut down or inadequate initialization.
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公开(公告)号：US09773078B2
公开(公告)日：2017-09-26
申请号：US14602580
申请日：2015-01-22
申请人： Synopsys, Inc.
CPC分类号： G06F17/5027 , G06F17/5081
摘要： Embodiments relate to the emulation of circuits, and representation of unknown states of signals. A disclosed system (and method and computer program product) includes an emulation environment to convert a digital signal of a DUT in a form capable of representing an unknown state. In addition, the disclosed system converts digital logic circuits such as Boolean logic, flip flops, latches, and memory circuits to be operable with signals having unknown states. Thus, an unknown state of a signal is indicated and propagated through digital logic circuits represented in a disclosed semantic to enable prompt detection of improper operation of the DUT, for example, due to power shut down or inadequate initialization.
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4.发明授权公开(公告)号：US11868694B1
公开(公告)日：2024-01-09
申请号：US16874197
申请日：2020-05-14
申请人： Synopsys, Inc.
IPC分类号： G06F30/3312 , G06F119/12
CPC分类号： G06F30/3312 , G06F2119/12
摘要： A system is disclosed that includes a memory, and a processor configured to perform operations stored in the memory. The processor performs the operations to analyze each of a first set of sequential elements of a plurality of sequential elements to determine an edge of a clock signal pattern of a clock associated with each of the first set of sequential elements causing an output change at corresponding one or more sequential elements of the first set of sequential elements. The processor further performs the operations to discard one or more cycles of the clock signal pattern of the clock from emulation that do not include the edge of the clock signal pattern that causes at least one sequential element of the first set of sequential elements to change the output and emulate remaining cycles of the clock signal pattern of the clock.
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5.发明授权公开(公告)号：US10949589B2
公开(公告)日：2021-03-16
申请号：US15982997
申请日：2018-05-17
申请人： Synopsys, Inc.
IPC分类号： G06F30/3312 , G06F30/34 , G06F30/331 , G06F30/3323 , G06F30/396 , G06F111/04 , G06F111/20 , G06F119/12
摘要： The independent claims of this patent signify a concise description of embodiments. A hardware emulation system is configured to define a variable delay associated with each of a multitude of design clocks used in the circuit design, compute a compression value in accordance with the multitude of variable delays, detect a change in one or more of the variable delays, and recompute the time compression value in response to the detected change. The hardware emulation system is further configured to recompute the time compression using programmable circuitry disposed in the hardware emulation system and without stopping the hardware emulation system. Such circuitry may be disposed in a single programmable device disposed in the hardware emulation system or a multitude of programmable devices disposed in the hardware emulation system. This Abstract is not intended to limit the scope of the claims.
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公开(公告)号：US10169505B2
公开(公告)日：2019-01-01
申请号：US15184266
申请日：2016-06-16
申请人： Synopsys, Inc.
IPC分类号： G06F17/50
摘要： A computer-implemented method for configuring a hardware verification system includes receiving, in the computer, a first data representative of a first design. The method further includes performing a first mapping of the first data to generate a second data in accordance with a first cost function and one or more first delays each associated with a different one of a first multitude of paths. One of the first multitude of paths includes a critical path characterized by a second delay. The method further includes performing a second mapping of the second data to generate a third data in accordance with a second cost function and a multitude of third delays each associated with a different one of a second multitude of paths and the second delay. The method further includes compiling the third data for configuring the hardware verification system.
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7.发明申请公开(公告)号：US20180336304A1
公开(公告)日：2018-11-22
申请号：US15982997
申请日：2018-05-17
申请人： Synopsys, Inc.
IPC分类号： G06F17/50
摘要： The independent claims of this patent signify a concise description of embodiments. A hardware emulation system is configured to define a variable delay associated with each of a multitude of design clocks used in the circuit design, compute a compression value in accordance with the multitude of variable delays, detect a change in one or more of the variable delays, and recompute the time compression value in response to the detected change. The hardware emulation system is further configured to recompute the time compression using programmable circuitry disposed in the hardware emulation system and without stopping the hardware emulation system. Such circuitry may be disposed in a single programmable device disposed in the hardware emulation system or a multitude of programmable devices disposed in the hardware emulation system. This Abstract is not intended to limit the scope of the claims.
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公开(公告)号：US20170109466A1
公开(公告)日：2017-04-20
申请号：US15083807
申请日：2016-03-29
申请人： Synopsys, Inc.
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F17/504 , G06F2217/62
摘要： A computer-implemented method for configuring a hardware verification system is presented. The method includes receiving, in the computer, a first data representative of a first design including a first sequential element configured to be evaluated in accordance with a first signal, when the computer is invoked to configure the verification system. The method further includes transforming, using the computer, the first data into a second data representative of a second design. The second data includes a third data associated with a second sequential element including functionality of the first sequential element and a fourth data associated with a first logic circuit. The evaluation of the second sequential element at cycle i of the hardware verification system is performed in accordance with the first logic circuit and a value of the first signal as computed during cycle i−1 of the hardware verification system when the second data is compiled for programming into the hardware verification system, where i is an integer number.
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公开(公告)号：US10185794B2
公开(公告)日：2019-01-22
申请号：US15083807
申请日：2016-03-29
申请人： Synopsys, Inc.
IPC分类号： G06F17/50
摘要： A computer-implemented method for configuring a hardware verification system is presented. The method includes receiving a first data representative of a first design including a first sequential element configured to be evaluated in accordance with a first signal. The method further includes transforming the first data into a second data representative of a second design. The second data includes a third data associated with a second sequential element including functionality of the first sequential element and a fourth data associated with a first logic circuit. The evaluation of the second sequential element at cycle i of the hardware verification system is performed in accordance with the first logic circuit and a value of the first signal as computed during cycle i−1 of the hardware verification system when the second data is compiled for programming into the hardware verification system, where i is an integer number.
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公开(公告)号：US09858398B2
公开(公告)日：2018-01-02
申请号：US14929112
申请日：2015-10-30
申请人： Synopsys, Inc.
CPC分类号： G06F21/14 , G06F21/606 , G06F2221/0724
摘要： Multiple computer systems each include at least one EDA tool that performs certain EDA functions. Each computer system also includes source code of a design with the names of source code elements and an encoding module that generates unique identifiers for the source code elements according to a specific encoding algorithm. The encoding module identifies each source code element included in the source code. For each source code element, the encoding module generates a unique identifier by applying the encoding algorithm to the name of the element. When electronic design information is going to be transmitted to another computer system and the electronic design information includes source code elements, the encoding module encodes the information by replacing each source code element with the unique identifier generated for the element.
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