公开(公告)号：US20240361385A1

公开(公告)日：2024-10-31

申请号：US18767186

申请日：2024-07-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Anshuman Chandra ,  Sandeep Kumar Goel

IPC分类号： G01R31/3185 ,  G01R31/3187

CPC分类号： G01R31/318572 ,  G01R31/318536 ,  G01R31/318547 ,  G01R31/318555 ,  G01R31/3187

摘要： Systems, methods, and devices are described herein for performing intra-die and inter-die tests of one or more dies of an integrated circuit. A cell of an integrated circuit includes a data register, an I/O pad, and a first multiplexer. The data register is configured to output a signal. The I/O pad is coupled to the data register and configured to receive and buffer the signal. The first multiplexer is coupled to the I/O pad and the data register. The multiplexer is configured to selectively output either the buffered signal or the signal based on whether a scan mode or a functional mode is enabled.

公开(公告)号：US20240319268A1

公开(公告)日：2024-09-26

申请号：US18189859

申请日：2023-03-24

申请人： QUALCOMM Incorporated

发明人： Gaurav VERMA ,  Saksham TANDON

IPC分类号： G01R31/317 ,  B60L3/00 ,  G01R31/3183 ,  G01R31/3187 ,  G06F11/27 ,  G11C29/16

CPC分类号： G01R31/31724 ,  B60L3/0084 ,  G01R31/318335 ,  G01R31/3187 ,  G06F11/27 ,  G11C29/16

摘要： Aspects of the present disclosure provide a method generally including obtaining one or more built-in self-test (BIST) patterns, each pattern including a series of instructions, applying a compression scheme to generate one or more compressed BIST patterns, wherein the compression scheme encodes an operation and data field of instructions to generate encoded instructions, each encoded instruction having an identifier (ID) field and a variable number of data bytes, wherein the ID field identifies a type of the operation and indicates the variable number of data bytes, and storing the compressed BIST patterns.

公开(公告)号：US12092689B2

公开(公告)日：2024-09-17

申请号：US17545113

申请日：2021-12-08

申请人： Qorvo US, Inc.

发明人： Alexander Wayne Hietala ,  Christopher Truong Ngo ,  Ryan Lee Bunch

IPC分类号： G01R31/3177 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/3187 ,  G11C29/32 ,  G11C29/56

CPC分类号： G01R31/3177 ,  G01R31/2851 ,  G01R31/2884 ,  G01R31/31712 ,  G01R31/31713 ,  G01R31/31724 ,  G01R31/318572 ,  G01R31/3187 ,  G11C29/32 ,  G11C2029/5602

摘要： A Scan test in a single-wire bus circuit is described in the present disclosure. The single-wire bus circuit has only one external pin for connecting to a single-wire bus. Given that multiple physical pins are required to carry out the Scan test, the single-wire bus circuit must provide additional pins required by the Scan test. In embodiments disclosed herein, the single-wire bus circuit includes a communication circuit under test, and a driver circuit coupled to the communication circuit via multiple internal pins. The driver circuit uses a subset of the internal pins as input pins and another subset of the internal pins as output pins to carry out the Scan test in the communication circuit. As a result, it is possible to perform the Scan test without adding additional external pins to the single-wire bus circuit, thus helping to reduce complexity and footprint of the single-wire bus circuit.

公开(公告)号：US20240302432A1

公开(公告)日：2024-09-12

申请号：US18597499

申请日：2024-03-06

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Hobin SONG ,  Juyun Lee ,  Jiyoung Kim ,  Jaehyun Park ,  Sooeun Lee ,  Insik Hwang

IPC分类号： G01R31/3183 ,  G01R31/317 ,  G01R31/3187 ,  H03K5/00 ,  H03K5/13 ,  H03L7/08 ,  H03L7/081

CPC分类号： G01R31/318328 ,  G01R31/31724 ,  G01R31/3187 ,  H03K5/13 ,  H03L7/0807 ,  H03K2005/00052 ,  H03L7/0812

摘要： A system-on-chip includes a clock generation circuit configured to generate a reference clock of a first phase; a transmission circuit comprising a serializer configured to serialize data according to the reference clock of the first phase; a reception circuit comprising a clock data recovery (CDR) circuit configured to receive the serialized data and generate a first recovery clock and recovery data; and a Built In Self Test (BIST) circuit including a CDR performance monitoring circuit configured to generate a control signal provided to a delay controller configured to delay a clock signal by a preset phase difference, and the delay controller configured to delay the clock signal in response to the control signal by the preset phase difference and provide the delayed clock signal to the transmission circuit.

公开(公告)号：US12074543B2

公开(公告)日：2024-08-27

申请号：US17764823

申请日：2020-10-06

申请人： Knorr-Bremse Systeme Fuer Nutzfahrzeuge GmbH

发明人： Ali Terro ,  Kai-Sven Becker ,  Zeger Bontinck

IPC分类号： G01R31/3187 ,  G01R31/34 ,  H02P23/14 ,  H02P29/60

CPC分类号： H02P23/14 ,  G01R31/343 ,  H02P29/60

摘要： A method and equipment (apparatus) for estimating motor parameters includes: receiving an operating parameter of an electric motor, estimating an estimated first motor parameter based on the operating parameter and on an initially determined second motor parameter and estimating an estimated second motor parameter based on the operating parameter and on an initially determined first motor parameter. The equipment (apparatus) and the method further include estimating a revised estimated second motor parameter based on the estimated first motor parameter and on the operating parameter, and estimating a revised estimated first motor parameter based on the estimated second motor parameter and on the operating parameter.

公开(公告)号：US12025662B1

公开(公告)日：2024-07-02

申请号：US18113547

申请日：2023-02-23

申请人： Avago Technologies International Sales Pte. Limited

发明人： Shengyuan Li ,  Xicheng Jiang

IPC分类号： G01R31/3187 ,  G01R31/317 ,  G01R31/3177

CPC分类号： G01R31/3187 ,  G01R31/31727 ,  G01R31/3177

摘要： A circuit includes first and second power devices that include first and second field effect transistors (FET). A first channel is located between a first drain and a first source of first FET and a second channel is located between a second drain and a second source of second FET. First and second drains are coupled to first common junction and first and second sources are coupled to second common junction. The first common junction is configured to receive a current. A switch controller is coupled to a first gate of the first FET and to a second gate of the second FET to apply a bias voltage to the first and second gates one by one and in turn. An analog to digital converter coupled to first common junction and second common junction and configured to alternately digitize a voltage of the first channel or the second channel.

公开(公告)号：US12025659B2

公开(公告)日：2024-07-02

申请号：US18047511

申请日：2022-10-18

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Prasanth Viswanathan Pillai ,  Rajeev Suvarna ,  Saya Goud Langadi ,  Shailesh Ganapat Ghotgalkar

IPC分类号： G06F3/06 ,  G01R31/3177 ,  G01R31/3185 ,  G01R31/3187 ,  G06F11/10 ,  G06F12/0804 ,  G06F13/16 ,  H03K3/037 ,  H03K5/24 ,  H03K19/003

CPC分类号： G01R31/3177 ,  G01R31/3187 ,  H03K3/037 ,  H03K5/24 ,  H03K19/003 ,  G01R31/318566

摘要： Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.

公开(公告)号：US11961575B2

公开(公告)日：2024-04-16

申请号：US17942059

申请日：2022-09-09

申请人： SambaNova Systems, Inc.

发明人： Thomas A. Ziaja ,  Uma Durairajan ,  Dinesh R. Amirtharaj

IPC分类号： G11C29/32 ,  G11C7/10 ,  G11C29/12 ,  G11C29/36 ,  G11C29/42 ,  G01R31/317 ,  G01R31/3177 ,  G01R31/3185 ,  G01R31/3187 ,  G06F11/27 ,  G11C7/22 ,  G11C11/408

CPC分类号： G11C29/32 ,  G11C7/1039 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/36 ,  G11C29/42 ,  G01R31/3172 ,  G01R31/31723 ,  G01R31/3177 ,  G01R31/3185 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/318566 ,  G01R31/3187 ,  G06F11/27 ,  G11C7/1051 ,  G11C7/22 ,  G11C11/4082 ,  G11C2029/3202

摘要： An integrated circuit (IC) includes first and scan latches that are enabled to load data during a first part of a clock period. A clocking circuit outputs latch clocks with one latch clock driven to an active state during a second part of the clock period dependent on a first address input. A set of storage elements have inputs coupled to the output of the first scan latch and are respectively coupled to a latch clock to load data during a time that their respective latch clock is in an active state. A selector circuit is coupled to outputs of the first set of storage elements and outputs a value from one output based on a second address input. The second scan latch then loads data from the selector's output during the first part of the input clock period.

公开(公告)号：US11940495B1

公开(公告)日：2024-03-26

申请号：US18352164

申请日：2023-07-13

申请人： PseudolithIC, Inc.

发明人： James Buckwalter ,  Michael Hodge ,  Justin Kim ,  Daniel Green ,  Florian Herrault

IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/3187

CPC分类号： G01R31/3187 ,  G01R31/31704 ,  G01R31/318511 ,  G01R31/318513

摘要： An electronic assembly has a host wafer having a first circuit including wafer transistors and passive, non-transistor devices. Chiplets have a second circuit including at least one radio frequency (RF) transistor device. Electrical interconnects are between the chiplets and wafer. The electrical interconnects electrically connect the first circuit to the second circuits. Oscillators that have the wafer transistor, the RF transistor and the electrical interconnects produce a signal for built-in self-test circuits for testing an assembly design of the electronic assembly and speeds of the RF chiplet transistors.

公开(公告)号：US11899062B2

公开(公告)日：2024-02-13

申请号：US17605637

申请日：2019-12-24

申请人： NEC Space Technologies, Ltd.

发明人： Hiroki Hihara

IPC分类号： G01R31/3177 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/3187 ,  G01R31/28 ,  G06F11/16 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

CPC分类号： G01R31/3177 ,  G01R31/28 ,  G01R31/3187 ,  G01R31/31724 ,  G01R31/318519 ,  G06F11/16 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

摘要： A basic logic element includes: a calculation unit configured to perform calculation processing; a self-diagnosis unit configured to self-diagnose whether or not there is an abnormality in a result of the calculation output from the basic logic element; a management unit configured to determine whether or not to retain authority to output the result of the calculation based on a result of the diagnosis performed by the self-diagnosis unit and output a result of the determination as an authority signal; and an output control unit configured to control whether or not to output the result of the calculation performed by the calculation unit based on whether or not the authority to output data is retained by the management unit.