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101 条记录 (耗时 0.035 秒)

    Symbol timing search algorithm
    1.
    发明申请
    Symbol timing search algorithm 有权
    符号定时搜索算法

    公开(公告)号：US20050254611A1

    公开(公告)日：2005-11-17

    申请号：US10511640

    申请日：2003-04-15

    申请人： Weixiao Liu ,  Aaron Bouillet ,  Matthew Mayer

    发明人： Weixiao Liu ,  Aaron Bouillet ,  Matthew Mayer

    IPC分类号： H04N5/12 ,  H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04L7/08 ,  H04L27/02 ,  H04N7/62

    CPC分类号： H04L7/0054 ,  H04L7/0004 ,  H04L7/0062 ,  H04L7/0083 ,  H04L7/0334 ,  H04L7/0335 ,  H04L7/08 ,  H04L27/02 ,  H04N21/438 ,  H04N21/44209

    摘要： A system is described for establishing timing synchronism between a local receiver symbol clock and a transmitter symbol clock. A prescribed number of offset values are calculated for desired symbol timing range, the offset values being grouped substantially symmetrically about a central offset value. Each of the preselected offset values are tested to see if symbol timing recovery lock can be achieved by starting at the central offset value and gradually moving away from such value. Finally, two timing detection algorithms are used and switched between the two algorithms is carried out as desired to maximize the possibility of STR lock.

    摘要翻译： 描述了一种用于建立本地接收符号时钟和发射机符号时钟之间的定时同步的系统。 针对期望的符号定时范围计算规定数量的偏移值，偏移值基于中心偏移值基本对称地分组。 测试每个预选偏移值，以查看是否可以通过从中心偏移值开始并逐渐离开此值来实现符号定时恢复锁定。 最后，使用两种定时检测算法，并根据需要进行两种算法之间的切换，以最大化STR锁定的可能性。

    Apparatus and method for reproducing picture signal
    2.
    发明授权
    Apparatus and method for reproducing picture signal 失效
    用于再现图像信号的装置和方法

    公开(公告)号：US06892025B2

    公开(公告)日：2005-05-10

    申请号：US09819203

    申请日：2001-03-28

    申请人： Motoi Togashi ,  Ryoji Yamaguchi ,  Tsutomu Hashimoto ,  Ken Monda ,  Keiichi Miyazaki

    发明人： Motoi Togashi ,  Ryoji Yamaguchi ,  Tsutomu Hashimoto ,  Ken Monda ,  Keiichi Miyazaki

    IPC分类号： H04N5/92 ,  G11B20/10 ,  H04N7/62 ,  H04N19/00 ,  H04N19/44 ,  H04N19/46 ,  H04N19/65 ,  H04N19/70 ,  H04N19/89 ,  H04N5/85 ,  H04N7/26

    CPC分类号： H04N21/4325 ,  H04N21/4135 ,  H04N21/4305 ,  H04N21/4334 ,  H04N21/4348

    摘要： A picture signal reproducing apparatus for synchronously reproducing a variety of digital coded data strings, comprises: data transmission controlling unit for inputting a series of digital multiplexed coded data strings including a plurality of packs connected with each other in serial, each of the packs having a SCR, and inserting a reproduction unit switching information at a seamless point between two packs in the series of digital multiplexed coded data strings according to the SCR for each of the packs; and reproduction controlling unit for detecting the seamless point on the basis of the reproduction unit switching information from the series of digital multiplexed coded data strings to synchronously reproduce the variety of digital coded data strings at the detected seamless point.

    摘要翻译： 一种用于同步再现各种数字编码数据串的图像信号再现装置，包括：数据传输控制单元，用于输入包括串联连接的多个数据包的一系列数字多路复用编码数据串，每个数据包具有 SCR，并且根据用于每个包的SCR的数字多路复用编码数据串系列中的两个包之间的无缝点处插入再现单元切换信息; 以及再现控制单元，用于基于来自所述一系列数字多路复用编码数据串的再现单元切换信息来检测无缝点，以在检测到的无缝点处同步再现各种数字编码数据串。

    Digital transmission system and clock reproducing device
    3.
    发明申请
    Digital transmission system and clock reproducing device 失效
    数字传输系统和时钟再生装置

    公开(公告)号：US20050058158A1

    公开(公告)日：2005-03-17

    申请号：US10910908

    申请日：2004-08-04

    申请人： Masaru Miyamoto

    发明人： Masaru Miyamoto

    IPC分类号： H04N5/04 ,  G11B20/10 ,  G11B20/14 ,  H03L7/087 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H04J3/06 ,  H04L7/033 ,  H04N5/60 ,  H04N7/08 ,  H04N7/081 ,  H04N7/62

    CPC分类号： H03L7/113 ,  H03L7/087 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/06 ,  H04J3/0685 ,  H04N5/602 ,  H04N21/4122 ,  H04N21/4305

    摘要： Letting fp be the frequency of a pixel clock, fs be the audio sampling frequency, and fa be the frequency of an audio clock to be reproduced, fa=384fs=(N/M)fp, where N and M are frequency dividing ratios between the pixel clock and the audio clock of a frequency corresponding to the audio sampling frequency. When fs=48 kHz, M=27000 and N=18432, and when fs=44.1 kHz, M=30000 and N=18816. A VCO control unit detects a change in the audio sampling frequency fs from a control voltage Vctl output from a loop filter or from the frequency fo of an output clock of an oscillating unit, and then selects one of at least two VCOs.

    摘要翻译： 令fp是像素时钟的频率，fs是音频采样频率，fa是要再现的音频时钟的频率，fa = 384fs =（N / M）fp，其中N和M是 像素时钟和与音频采样频率对应的频率的音频时钟。 当fs = 48kHz时，M = 27000，N = 18432，当fs = 44.1kHz时，M = 30000，N = 18816。 VCO控制单元从环路滤波器输出的控制电压Vct1或振荡单元的输出时钟的频率fo检测音频采样频率fs的变化，然后选择至少两个VCO中的一个。

    System and method for audio/video synchronization
    4.
    发明申请
    System and method for audio/video synchronization 有权
    用于音频/视频同步的系统和方法

    公开(公告)号：US20050018775A1

    公开(公告)日：2005-01-27

    申请号：US10892897

    申请日：2004-07-16

    申请人： Mk Subramanian ,  Sandeep Bhatia ,  Santosh Savekar ,  Gaurav Aggarwal ,  K. Shivapirakasan

    发明人： Mk Subramanian ,  Sandeep Bhatia ,  Santosh Savekar ,  Gaurav Aggarwal ,  K. Shivapirakasan

    IPC分类号： H04J3/00 ,  H04N7/12 ,  H04N7/173 ,  H04N7/62 ,  H04N11/02 ,  H04N11/04

    CPC分类号： H04N21/44004 ,  H04N21/4307

    摘要： Described herein is a system and method for audio visual synchronization. The picture are displayed by receiving an identifier, said identifier associated with a frame buffer storing a picture; extracting a presentation time stamp associated with the picture, wherein the picture is associated with a time stamp; comparing a local time clock value to the presentation time stamp; determining that the picture is mature for presentation if the presentation time stamp exceeds the local time clock value by less than a first predetermined threshold; and determining that the picture is mature for presentation if the local time clock value exceeds the presentation time stamp by less than a second predetermined threshold.

    摘要翻译： 这里描述了一种用于视听同步的系统和方法。 通过接收标识符显示图像，所述标识符与存储图像的帧缓冲器相关联; 提取与所述图片相关联的呈现时间戳，其中所述图片与时间戳相关联; 将本地时钟值与演示时间戳进行比较; 如果所述呈现时间戳超过所述本地时间时钟值小于第一预定阈值，则确定所述图片是成熟的; 以及如果所述本地时间时钟值超过所述呈现时间戳小于第二预定阈值，则确定所述图片是否成熟以进行呈现。

    Clock frequency synchronizer
    5.
    发明授权
    Clock frequency synchronizer 失效
    时钟频率同步器

    公开(公告)号：US6049886A

    公开(公告)日：2000-04-11

    申请号：US78252

    申请日：1998-05-13

    申请人： Hideyuki Motoyama

    发明人： Hideyuki Motoyama

    IPC分类号： H03L7/00 ,  H04L7/00 ,  H04N7/62 ,  G06F1/12

    CPC分类号： H04N21/4305

    摘要： Disclosed is a clock frequency synchronizer which receives a count value of system clock on an encoder side which is transmitted from the encoder as a reference count value, and generates system clock on a decoder side which is synchronous in frequency with the system clock on the encoder side on the basis of the reference count value. A counting means for counting the system clocks on the decoder side is provided, and the deviation of the frequency of the system clock on the decoder side from that of the system clock on the encoder side is obtained by using an increment .DELTA.C of the count value of the counting means during reference count value arrival interval .DELTA.T and the increment .DELTA.P of the reference count value. The frequency of the system clock on the decoder side is so controlled that the frequency deviation becomes zero.

    摘要翻译： 公开了一种时钟频率同步器，其接收从编码器发送的编码器侧的系统时钟的计数值作为基准计数值，并且在解码器侧生成与编码器上的系统时钟频率同步的系统时钟 根据参考计数值。 提供了用于对解码器侧的系统时钟进行计数的计数装置，并且通过使用计数器的增量DELTA C来获得解码器侧的系统时钟频率与编码器侧的系统时钟频率的偏差 在参考计数值到达间隔DELTA T期间计数装置的值和参考计数值的增量DELTA P。 解码器侧的系统时钟的频率受到如此控制，使得频率偏差变为零。

    Synchronizing device with head word position verification
    6.
    发明授权
    Synchronizing device with head word position verification 失效
    同步装置与头字位置验证

    公开(公告)号：US6047004A

    公开(公告)日：2000-04-04

    申请号：US964354

    申请日：1997-11-04

    申请人： Masayuki Koyama

    发明人： Masayuki Koyama

    IPC分类号： H04L7/04 ,  H04J3/06 ,  H04L7/08 ,  H04L7/10 ,  H04L12/70 ,  H04N7/62 ,  H04J3/07

    CPC分类号： H04N21/4302 ,  H04N21/242 ,  H04L7/0008 ,  H04L7/042 ,  H04L7/08 ,  H04L7/10

    摘要： From an input data signal (Data.sub.-- In) formed of a data signal complied with the MPEG standard including unit packets each formed of a sequence of 204 pieces of 8-bit-long unit data assigned in a sequence of 6-bit-long unit data, the original packet-unit data signal is reconfigured. Data having a length of 8 bits are sequentially extracted from two 6-bit-long unit data successively held in buffers (BS1, BS2). Correctness of the position of the head word of the packet is verified on the basis of whether a synchronizing code (Cd) indicating the head word repeatedly appears in the cycles of packets. It is determined whether a cycle of a packet has passed on the basis of a value counted in synchronization with an extraction signal (Dout), eliminating the necessity for the FIFO required in conventional devices. As a result, size reduction and cost reduction of the device are implemented.

    摘要翻译： 从由符合MPEG标准的数据信号形成的输入数据信号（Data-In）包括单元分组，每个单元分组由以6位长单位序列分配的204个8位长单元数据的序列形成 数据，原始分组单元数据信号被重新配置。 从连续保存在缓冲器（BS1，BS2）中的两个6位长的单位数据顺序提取长度为8位的数据。 基于分组循环中是否重复出现表示头字的同步码（Cd），来验证分组的头字的位置的正确性。 基于与提取信号（Dout）同步计数的值来确定分组的周期是否已经过去，消除了传统设备中所需的FIFO的必要性。 结果，实现了设备的尺寸减小和成本降低。

    Image decoder for decoding variable-length image data using frame synchronizing signal and method of decoding the image data
    8.
    发明授权
    Image decoder for decoding variable-length image data using frame synchronizing signal and method of decoding the image data 失效
    用于使用帧同步信号解码可变长度图像数据的图像解码器和对图像数据进行解码的方法

    公开(公告)号：US5798804A

    公开(公告)日：1998-08-25

    申请号：US596503

    申请日：1996-02-05

    申请人： Hiromi Okitsu

    发明人： Hiromi Okitsu

    IPC分类号： G06F5/06 ,  H03M7/40 ,  H04N7/62 ,  H04N19/00 ,  H04N19/423 ,  H04N19/625 ,  H04N19/85 ,  H04N19/91 ,  H04N7/64 ,  H04N7/26

    CPC分类号： H04N21/4302 ,  H04N19/44 ,  H04N19/61 ,  H04N21/44004 ,  H04N19/13 ,  H04N19/91

    摘要： In an image decoder of MPEG system or the like, a delay buffer which is able to store data which corresponds to at least one frame is provided in the rear stage of an input buffer which is normally provided, and a frame synchronizing pulse is applied to determine the timing of display independently of that which is determined by the bit stream. In synchronization with the frame synchronizing pulse which occurs for the first time after the passage of a delay period set for every frame in each of the bit streams, that frame is displayed. The input bit streams coming in during the period of time which elapses from the passage of the delay period until the occurrence of the frame synchronizing pulse, are absorbed by the delay buffer.

    摘要翻译： 在MPEG系统等的图像解码器中，能够存储对应于至少一帧的数据的延迟缓冲器被提供在正常提供的输入缓冲器的后级中，并且帧同步脉冲被应用于 确定独立于由比特流确定的定时的显示时间。 与在每个比特流中为每个帧设置的延迟时间段通过之后第一次发生的帧同步脉冲同步地，显示该帧。 在从延迟周期到帧同步脉冲的发生经过的时间段内进入的输入比特流被延迟缓冲器吸收。