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    Comparator circuit
    1.
    发明授权
    Comparator circuit 失效
    比较器电路

    公开(公告)号：US08610465B2

    公开(公告)日：2013-12-17

    申请号：US12993145

    申请日：2009-05-25

    Applicant: Christer Jansson

    Inventor： Christer Jansson

    IPC: H03K5/22

    CPC classification number: H03F3/45753 ,  H03F2203/45292 ,  H03F2203/45444 ,  H03F2203/45538 ,  H03F2203/45634

    Abstract: A comparator circuit (5) comprising a fully differential main amplifier unit (10, 10b). The main amplifier unit (10, 10b) comprises a control port and is adapted to control a bias current of a first branch of the main amplifier unit (10, 10b) and/or a bias current of a second branch of the main amplifier unit (10, 10b) in response to one or more control voltages supplied to the control port of the main amplifier unit (10, 10b). The comparator circuit (5) comprises circuitry (60) for balancing the voltages at the positive and negative input terminals (12a, 12b) of the main amplifier unit (10, 10b) during a first clock phase of the comparator circuit (5). Furthermore, the comparator circuit (10, 10a) comprises a switched-capacitor accumulator unit with a differential input. The switched-capacitor accumulator unit is operatively connected to the positive and negative output terminals (14a, 14b) of the main amplifier unit (10, 10b) for sampling voltages at the positive and negative output terminals (14a, 14b) of the main amplifier unit (10, 10b) during the first clock phase, and operatively connected to the control port of the main amplifier unit (10, 10b) for supplying said one or more control voltages.

    Abstract translation: 一种包括全差分主放大器单元（10,10b）的比较器电路（5）。 主放大器单元（10,10b）包括控制端口，并且适于控制主放大器单元（10,10b）的第一支路的偏置电流和/或主放大器单元的第二支路的偏置电流 （10,10b），响应于提供给主放大器单元（10,10b）的控制端口的一个或多个控制电压。 比较器电路（5）包括用于在比较器电路（5）的第一时钟相位期间平衡主放大器单元（10,10b）的正和负输入端（12a，12b）处的电压的电路（60）。 此外，比较器电路（10,10a）包括具有差分输入的开关电容器累加器单元。 开关电容器蓄电单元可操作地连接到主放大器单元（10,10b）的正输出端和负输出端（14a，14b），用于对主放大器的正负输出端（14a，14b）采样电压 单元（10,10b），并且可操作地连接到主放大器单元（10,10b）的控制端口，用于提供所述一个或多个控制电压。

    Receiver for a Differential Data Bus
    2.
    发明申请
    Receiver for a Differential Data Bus 有权
    差分数据总线接收器

    公开(公告)号：US20080265969A1

    公开(公告)日：2008-10-30

    申请号：US11632031

    申请日：2005-06-30

    Applicant: Jelle Nico Wolthek ,  Cornelis Klaas Waardenburg ,  Cecilius Gerardus Kwakernaat ,  Stefan Gerhard Erich Butselaar

    Inventor： Jelle Nico Wolthek ,  Cornelis Klaas Waardenburg ,  Cecilius Gerardus Kwakernaat ,  Stefan Gerhard Erich Butselaar

    IPC: H03L5/00

    CPC classification number: H04L25/0296 ,  H03F3/45991 ,  H03F2203/45538 ,  H03F2203/45588 ,  H03F2203/45616 ,  H04L25/0274

    Abstract: The invention relates to a receiver for a differential bus with a switch control logic (151), with two branches with resistive elements (7, 61 . . . 70, 8 and 5, 11 . . . 20, 6) and with switches (3, 80) for switching the resistive elements, in which the switch control logic sets the switches—in a first routine for determining the absolute level of signals on the bus by applying a common mode voltage to the bus, by comparing the voltage on a first resistive branch with a reference voltage, by selecting the correct switch settings, and by writing these settings to an internal storage device, —and in a second routine for minimizing the mismatch between the two resistive branches by applying a common mode voltage to the bus, by comparing the voltage of the second resistive branch with that of the already trimmed first resistive branch, by selecting the correct switch settings for the second branch, and by writing these settings to an internal storage device. The receiver therefore provides good balancing and common mode rejection.

    Abstract translation: 本发明涉及一种具有开关控制逻辑（151）的差分总线的接收器，其具有两个具有电阻元件（7,61。，70,8和5,11，...，20,6）的分支以及开关（ 3，80），用于切换电阻元件，其中开关控制逻辑将开关设置在第一程序中，用于通过对总线施加共模电压来确定总线上的信号的绝对电平，通过比较 具有参考电压的第一电阻分支，通过选择正确的开关设置，以及将这些设置写入内部存储装置，以及在第二程序中，通过向总线施加共模电压来最小化两个电阻分支之间的失配 通过比较第二电阻分支的电压与已修整的第一电阻分支的电压，通过选择第二分支的正确开关设置，并将这些设置写入内部存储装置。 因此，接收机提供良好的平衡和共模抑制。

    Differential amplifier arrangement
    3.
    发明授权
    Differential amplifier arrangement 有权
    差分放大器布置

    公开(公告)号：US07327190B2

    公开(公告)日：2008-02-05

    申请号：US10573455

    申请日：2004-08-24

    Applicant: Paolo D'Abramo ,  Riccardo Serventi

    Inventor： Paolo D'Abramo ,  Riccardo Serventi

    IPC: H03F1/36

    CPC classification number: H03F3/45475 ,  H03F1/30 ,  H03F3/45991 ,  H03F2200/261 ,  H03F2203/45212 ,  H03F2203/45538 ,  H03F2203/45588

    Abstract: Circuitry for use in a differential amplifier includes an input stage having a first differential amplifier and an offset compensation stage that includes at least one controllable current source. The offset compensation stage is connected to a bias input of the first differential amplifier. The circuitry includes an output stage having a second differential amplifier, where the output stage is after an output of the input stage, and a programmable resistor network for controlling an amplification of the input stage. The programmable resistor network controls the amplification in accordance with a feedback from the first differential amplifier.

    Abstract translation: 用于差分放大器的电路包括具有第一差分放大器和包括至少一个可控电流源的偏移补偿级的输入级。 偏移补偿级连接到第一差分放大器的偏置输入。 电路包括具有第二差分放大器的输出级，其中输出级在输入级的输出之后，以及可编程电阻器网络，用于控制输入级的放大。 可编程电阻器网络根据来自第一差分放大器的反馈来控制放大。

    Differential amplifier circuit
    5.
    发明授权
    Differential amplifier circuit 失效
    差分放大电路

    公开(公告)号：US06252457B1

    公开(公告)日：2001-06-26

    申请号：US09472874

    申请日：1999-12-28

    Applicant: Takehiko Umeyama ,  Toru Takeuchi

    Inventor： Takehiko Umeyama ,  Toru Takeuchi

    IPC: H03F345

    CPC classification number: H03F3/45089 ,  H03F2203/45538 ,  H03F2203/45544 ,  H03F2203/45594 ,  H03F2203/45612 ,  H03F2203/45702

    Abstract: Emitters of a first NPN transistor and a second NPN transistor forming a differential input section are respectively connected to collectors of a third NPN transistor and a fourth NPN transistor; the collectors and bases of the third NPN transistor and the fourth NPN transistor are respectively connected through first and second capacitors; and the bases of the third NPN transistor and the fourth NPN transistor are respectively connected to a first reference power source through first and second resistors.

    Abstract translation: 形成差分输入部的第一NPN晶体管和第二NPN晶体管的发射极分别与第三NPN晶体管和第四NPN晶体管的集电极连接; 第三NPN晶体管和第四NPN晶体管的集电极和基极分别通过第一和第二电容器连接; 并且第三NPN晶体管和第四NPN晶体管的基极分别通过第一和第二电阻器连接到第一参考电源。

    Differential amplifier common-mode rejection ratio and gain trimming circuit
    7.
    发明授权
    Differential amplifier common-mode rejection ratio and gain trimming circuit 有权

    公开(公告)号：US11757417B2

    公开(公告)日：2023-09-12

    申请号：US17633555

    申请日：2020-04-30

    Applicant: SHANGHAI ANALOGY SEMICONDUCTOR TECHNOLOGY LTD.

    Inventor： Jun Zhang ,  Yi Du ,  Zhihao Yan

    IPC: H03F3/45

    CPC classification number: H03F3/45995 ,  H03F2203/45042 ,  H03F2203/45538 ,  H03F2203/45594

    Abstract: The present invention provides a common-mode rejection ratio and gain trimming circuit of differential amplifier, comprising: a first trimming unit and a second trimming unit coupled between an in-phase input voltage and a reference voltage, wherein the first trimming unit and the second trimming unit are coupled to a positive input terminal of the differential amplifier by means of tap switches; a third trimming unit and a fourth trimming unit coupled between tan inverting input voltage and an output terminal of the differential amplifier, wherein the third trimming unit and the fourth trimming unit are coupled to a negative input terminal of the differential amplifier by means of tap switches; wherein, the first trimming unit, the second trimming unit, the third trimming unit, and the fourth trimming unit comprise: a first trimming resistor string and a second trimming resistor string coupled in series; the first trimming resistor string is coupled in parallel with a first trimming auxiliary resistor string, and the second trimming resistor string is coupled in parallel with a second trimming auxiliary resistor string; wherein, the second trimming resistor string of the first trimming unit is coupled to the second trimming resistor string of the second trimming unit, and the second trimming resistor string of the third trimming unit is coupled to the second trimming resistor string of the fourth trimming unit.

    Ready-flag circuitry for differential amplifiers
    9.
    发明授权
    Ready-flag circuitry for differential amplifiers 有权
    差分放大器的就绪标志电路

    公开(公告)号：US09356569B2

    公开(公告)日：2016-05-31

    申请号：US14057886

    申请日：2013-10-18

    Applicant: Freescale Semiconductor, Inc.

    Inventor： Andre Luis Vilas Boas ,  Edevaldo Pereira Silva, Jr. ,  Pedro Barbosa Zanetta ,  Eduardo Ribeiro da Silva

    IPC: H03K5/153 ,  H03F3/45 ,  H03F1/30 ,  G05F3/30

    CPC classification number: H03F3/45192 ,  G05F3/30 ,  H03F1/301 ,  H03F2200/447 ,  H03F2203/45538

    Abstract: Ready-flag circuitry for differential amplifiers. In some embodiments, a semiconductor device may include an amplifier including two inputs, and a ready-flag circuit operably coupled to the amplifier, the ready-flag circuit configured to monitor two or more internal nodes of the amplifier and to produce a signal indicating whether a voltage or current difference between the two inputs has been minimized. In other embodiments, a method may include monitoring, via a ready-flag circuit, a first and a second internal node of a differential amplifier, wherein the differential amplifier is part of a bandgap voltage reference circuit and producing, via the ready-flag circuit, a signal indicating whether an output of the bandgap voltage reference circuit has reached a nominal value.

    Abstract translation: 差分放大器的就绪标志电路。 在一些实施例中，半导体器件可以包括具有两个输入的放大器和可操作地耦合到放大器的就绪标志电路，准备标志电路被配置为监视放大器的两个或更多个内部节点并产生指示是否 两个输入之间的电压或电流差已被最小化。 在其他实施例中，一种方法可以包括经由就绪标志电路监测差分放大器的第一和第二内部节点，其中差分放大器是带隙电压参考电路的一部分，并且经由就绪标志电路 指示带隙电压基准电路的输出是否已经达到标称值的信号。

    READY-FLAG CIRCUITRY FOR DIFFERENTIAL AMPLIFIERS
    10.
    发明申请
    READY-FLAG CIRCUITRY FOR DIFFERENTIAL AMPLIFIERS 有权
    用于差分放大器的准直电路

    公开(公告)号：US20150109054A1

    公开(公告)日：2015-04-23

    申请号：US14057886

    申请日：2013-10-18

    Applicant: Freescale Semiconductor, Inc.

    Inventor： Andre Luis Vilas Boas ,  Edevaldo Pereira Silva, JR. ,  Pedro Barbosa Zanetta ,  Eduardo Ribeiro da Silva

    IPC: H03F3/45 ,  H03F1/00

    CPC classification number: H03F3/45192 ,  G05F3/30 ,  H03F1/301 ,  H03F2200/447 ,  H03F2203/45538

    Abstract: Ready-flag circuitry for differential amplifiers. In some embodiments, a semiconductor device may include an amplifier including two inputs, and a ready-flag circuit operably coupled to the amplifier, the ready-flag circuit configured to monitor two or more internal nodes of the amplifier and to produce a signal indicating whether a voltage or current difference between the two inputs has been minimized. In other embodiments, a method may include monitoring, via a ready-flag circuit, a first and a second internal node of a differential amplifier, wherein the differential amplifier is part of a bandgap voltage reference circuit and producing, via the ready-flag circuit, a signal indicating whether an output of the bandgap voltage reference circuit has reached a nominal value.

    Abstract translation: 差分放大器的就绪标志电路。 在一些实施例中，半导体器件可以包括具有两个输入的放大器和可操作地耦合到放大器的就绪标志电路，准备标志电路被配置为监视放大器的两个或更多个内部节点并产生指示是否 两个输入之间的电压或电流差已被最小化。 在其他实施例中，一种方法可以包括经由就绪标志电路监测差分放大器的第一和第二内部节点，其中差分放大器是带隙电压参考电路的一部分，并且经由就绪标志电路 指示带隙电压基准电路的输出是否已经达到标称值的信号。

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