公开(公告)号：US09356569B2

公开(公告)日：2016-05-31

申请号：US14057886

申请日：2013-10-18

Applicant: Freescale Semiconductor, Inc.

Inventor： Andre Luis Vilas Boas ,  Edevaldo Pereira Silva, Jr. ,  Pedro Barbosa Zanetta ,  Eduardo Ribeiro da Silva

IPC: H03K5/153 ,  H03F3/45 ,  H03F1/30 ,  G05F3/30

CPC classification number: H03F3/45192 ,  G05F3/30 ,  H03F1/301 ,  H03F2200/447 ,  H03F2203/45538

Abstract: Ready-flag circuitry for differential amplifiers. In some embodiments, a semiconductor device may include an amplifier including two inputs, and a ready-flag circuit operably coupled to the amplifier, the ready-flag circuit configured to monitor two or more internal nodes of the amplifier and to produce a signal indicating whether a voltage or current difference between the two inputs has been minimized. In other embodiments, a method may include monitoring, via a ready-flag circuit, a first and a second internal node of a differential amplifier, wherein the differential amplifier is part of a bandgap voltage reference circuit and producing, via the ready-flag circuit, a signal indicating whether an output of the bandgap voltage reference circuit has reached a nominal value.

Abstract translation: 差分放大器的就绪标志电路。 在一些实施例中，半导体器件可以包括具有两个输入的放大器和可操作地耦合到放大器的就绪标志电路，准备标志电路被配置为监视放大器的两个或更多个内部节点并产生指示是否 两个输入之间的电压或电流差已被最小化。 在其他实施例中，一种方法可以包括经由就绪标志电路监测差分放大器的第一和第二内部节点，其中差分放大器是带隙电压参考电路的一部分，并且经由就绪标志电路 指示带隙电压基准电路的输出是否已经达到标称值的信号。

公开(公告)号：US09467107B2

公开(公告)日：2016-10-11

申请号：US14203461

申请日：2014-03-10

Applicant: Freescale Semiconductor, Inc.

Inventor： Ricardo P. Coimbra ,  Edevaldo Pereira Silva, Jr. ,  Andre L. Couto

IPC: H03F3/45 ,  H03F1/42 ,  H03F3/30 ,  H03F3/50

CPC classification number: H03F3/3016 ,  H03F3/4521 ,  H03F3/505 ,  H03F2200/513 ,  H03F2200/69 ,  H03F2203/30091 ,  H03F2203/30123 ,  H03F2203/45274

Abstract: In some embodiments, a source follower circuit may include a first level shifter configured to receive an input voltage; an N-type Metal-Oxide-Semiconductor (NMOS) transistor having a gate terminal coupled to an output of the first level shifter; a second level shifter configured to receive the input voltage; a P-type Metal-Oxide-Semiconductor (PMOS) transistor having a gate terminal coupled to an output of the second level shifter and a source terminal coupled to a source terminal of the NMOS transistor; and an amplifier configured to receive the input voltage and to output a current at a node between the source terminal of the NMOS transistor and the source terminal of the PMOS transistor, wherein the current is determined based upon a difference between the input voltage and a reference voltage.

Abstract translation: 在一些实施例中，源跟随器电路可以包括被配置为接收输入电压的第一电平移位器; N型金属氧化物半导体（NMOS）晶体管，其具有耦合到所述第一电平移位器的输出的栅极端子; 配置为接收所述输入电压的第二电平移位器; 具有耦合到第二电平移位器的输出的栅极端子和耦合到NMOS晶体管的源极端子的源极的P型金属氧化物半导体（PMOS）晶体管; 以及放大器，被配置为接收所述输入电压并且在所述NMOS晶体管的源极端子和所述PMOS晶体管的源极端子之间的节点处输出电流，其中所述电流基于所述输入电压和参考值之间的差异来确定 电压。

公开(公告)号：US09194890B2

公开(公告)日：2015-11-24

申请号：US13890394

申请日：2013-05-09

Applicant: Freescale Semiconductor, Inc.

Inventor： Ricardo P. Coimbra ,  Edevaldo Pereira Silva, Jr.

IPC: H03K17/687 ,  G05F1/10 ,  G05F3/02 ,  G01R15/04

CPC classification number: G01R15/04

Abstract: Metal-Oxide-Semiconductor (MOS) voltage divider with dynamic impedance control. In some embodiments, a voltage divider may include two or more voltage division cells, each voltage division cell having a plurality of Metal-Oxide-Semiconductor (MOS) transistors, a least one of the plurality of MOS transistors connected to a signal path and at least another one of the plurality of MOS transistors connected to a control path, the voltage division cell configured to provide a voltage drop across the signal path based upon a control signal applied to the control path.

Abstract translation: 金属氧化物半导体（MOS）分压器，具有动态阻抗控制。 在一些实施例中，分压器可以包括两个或更多个分压单元，每个分压单元具有多个金属氧化物半导体（MOS）晶体管，多个MOS晶体管中的至少一个MOS晶体管连接到信号通路， 连接到控制路径的多个MOS晶体管中的至少另一个MOS晶体管被配置为基于施加到控制路径的控制信号跨越信号路径提供电压降。

公开(公告)号：US09588531B2

公开(公告)日：2017-03-07

申请号：US14714256

申请日：2015-05-16

Applicant: Freescale Semiconductor, Inc.

Inventor： Marcos M. Pelicia ,  Edevaldo Pereira Silva, Jr.

IPC: G05F1/575 ,  G05F1/46

CPC classification number: G05F1/575

Abstract: Voltage regulator with extended minimum to maximum current ratio. In some embodiments, a low-dropout (LDO) voltage regulator disposed within a semiconductor package may include an inner loop; and an outer loop coupled to the inner loop, wherein: the inner loop is configured to control a load response of the LDO voltage regulator and to reduce at least one of: a printed circuit board (PCB) effect on the outer loop, a packaging effect on the outer loop, or a parasitic effect on the outer loop; the outer loop is configured to control a voltage at an output of the LDO voltage regulator; the output of the LDO voltage regulator is coupled to an integrated circuit within the semiconductor package; and the PCB, package, and parasitic effects comprise inductive or resistive effects caused by elements disposed outside of the semiconductor package.

Abstract translation: 电压调节器具有最小到最大电流比。 在一些实施例中，设置在半导体封装内的低压差（LDO）电压调节器可以包括内环路; 以及外环，其耦合到所述内环，其中：所述内环被配置为控制所述LDO电压调节器的负载响应并且减少以下中的至少一个：在所述外环上的印刷电路板（PCB）效应， 对外环的影响，或对外环的寄生效应; 所述外部环路被配置为控制所述LDO稳压器的输出处的电压; LDO稳压器的输出耦合到半导体封装内的集成电路; 并且PCB，封装和寄生效应包括由设置在半导体封装外部的元件引起的电感或电阻效应。

公开(公告)号：US09459636B2

公开(公告)日：2016-10-04

申请号：US13774340

申请日：2013-02-22

Applicant: Freescale Semiconductor, Inc.

Inventor： Ivan Carlos Ribeiro Nascimento ,  Edevaldo Pereira Silva, Jr.

IPC: H02M3/156 ,  G05F1/10 ,  H02M1/00

CPC classification number: G05F1/10 ,  H02M3/156 ,  H02M2001/0025 ,  H02M2001/0045 ,  H02M2003/1566

Abstract: Systems and methods for transition control in a hybrid Switched-Mode Power Supply (SMPS). In some embodiments, a hybrid SMPS may include linear circuitry configured to produce an output voltage proportional to a variable duty cycle when the SMPS operates in linear mode and hysteretic circuitry coupled to the linear circuitry, the hysteretic circuitry configured to cause the duty cycle to assume one of two predetermined values when the SMPS operates in hysteretic mode. The hybrid SMPS may also include transition circuitry coupled to the linear circuitry and to the hysteretic circuitry, the transition circuitry configured to bypass at least a portion of the linear circuitry in response to the hybrid SMPS transitioning from the hysteretic mode to the linear mode.

Abstract translation: 混合开关电源（SMPS）中的转换控制系统和方法。 在一些实施例中，混合SMPS可以包括线性电路，其被配置为当SMPS以线性模式操作时产生与可变占空比成比例的输出电压，并且耦合到线性电路的滞后电路，所述滞后电路被配置为使占空比呈现 当SMPS以滞后模式工作时，两个预定值之一。 混合SMPS还可以包括耦合到线性电路和迟滞电路的转换电路，该转换电路被配置为绕过线性电路的至少一部分，以响应混合SMPS从滞后模式转换到线性模式。