公开(公告)号：US20160278382A1

公开(公告)日：2016-09-29

申请号：US14364321

申请日：2012-12-06

Applicant: Chuanxin SUN ,  Christer JANSSON

Inventor： Chuanxin Sun ,  Christer Jansson

IPC: A01N43/90 ,  C12N15/82

CPC classification number: A01N43/90 ,  A01N57/16 ,  A01N63/02 ,  A01N65/00 ,  C12N15/821 ,  C12N15/8218

Abstract: The invention relates to a method of producing transgenic plant material by transforming a plant with a vector comprising an essential gene having mutations at two sites at least. The method is exemplified with EPSPS as the essential gene. The method makes it possible to use an antisense molecule directed to the native form of said gene for selection of transformed plants. The application relates further to a plant obtainable by the method, a binary vector system containing the mutated essential gene, said mutations being silent mutations. Furthermore, the application discloses the use of an antisense molecule directed to an essential gene as a herbicide in particular using an aqueous solution comprising a saccharide such as sucrose, fructose and glucose.

Abstract translation: 本发明涉及通过用包含至少在两个位点具有突变的必需基因的载体转化植物来生产转基因植物材料的方法。 该方法以EPSPS为必需基因为例。 该方法使得可以使用针对所述基因的天然形式的反义分子来选择转化的植物。 本申请还涉及可通过该方法获得的植物，含有突变必需基因的二元载体系统，所述突变是沉默突变。 此外，本申请公开了使用指向必需基因的反义分子作为除草剂，特别是使用包含糖如蔗糖，果糖和葡萄糖的水溶液。

公开(公告)号：US08319526B2

公开(公告)日：2012-11-27

申请号：US12620156

申请日：2009-11-17

Applicant: Christer Jansson

Inventor： Christer Jansson

IPC: H03K5/22

CPC classification number: H03K5/2481

Abstract: A latched comparator circuit comprises an input amplification unit, a buffer unit, and a control unit. The input amplification unit comprises a first and a second input terminal for receiving a first and a second input voltage, respectively, of the latched comparator circuit. The input amplification unit further comprises a first and a second output terminal for outputting a first and a second output voltage, respectively, of the input amplification unit. In addition, the input amplification unit comprises a reset terminal arranged to receive a reset signal for resetting the input amplification unit. The buffer unit is operatively connected to the first and the second output terminal of the input amplification unit. Furthermore, the buffer unit comprises a first and a second output terminal for outputting a first and a second output voltage, respectively, of the buffer unit. The control unit is operatively connected to the input amplification unit and the buffer unit. The control unit is adapted to generate the reset signal based on the first and the second output voltage of the buffer unit and a clock signal and to generate an output signal of the latched comparator circuit based on the first and the second output voltage of the buffer unit. A method of operating the latched comparator circuit is also disclosed.

Abstract translation: 锁存比较器电路包括输入放大单元，缓冲单元和控制单元。 输入放大单元包括分别用于接收锁存比较器电路的第一和第二输入电压的第一和第二输入端。 输入放大单元还包括分​​别输出输入放大单元的第一和第二输出电压的第一和第二输出端。 此外，输入放大单元包括复位端子，其被配置为接收用于复位输入放大单元的复位信号。 缓冲单元可操作地连接到输入放大单元的第一和第二输出端。 此外，缓冲单元包括用于分别输出缓冲单元的第一和第二输出电压的第一和第二输出端。 控制单元可操作地连接到输入放大单元和缓冲单元。 控制单元适于基于缓冲单元的第一和第二输出电压和时钟信号产生复位信号，并且基于缓冲器的第一和第二输出电压产生锁存比较器电路的输出信号 单元。 还公开了一种操作锁存比较器电路的方法。

公开(公告)号：US08922406B2

公开(公告)日：2014-12-30

申请号：US14118412

申请日：2012-03-16

Applicant: Christer Jansson

Inventor： Christer Jansson

IPC: H03M1/10 ,  H03M1/06 ,  H03M1/46

CPC classification number: H03M1/1009 ,  H03M1/0692 ,  H03M1/1057 ,  H03M1/468

Abstract: A method of determining at least one calibration value for a redundant analog-to-digital-converter, ADC, is disclosed. For at least an i:th bit bL, the corresponding bit weight wi is less than the sum of the bit weights Wj, j=0, 1, . . . , i−1 corresponding to the bits bj, j=0, 1, . . . , i−1 with lesser significance than the bit bi. The method comprises sampling a first electrical value representative of the bit weight wi; performing a first analog-to-digital, A/D, conversion using the bits bj, j=0, 1, . . . , i−1 with lesser significance than the bit bi to obtain a first digital word of said bits bj, j=0, 1, . . . , i−1 with lesser significance than the bit bi representing said first electrical value; and estimating the value of the bit weight Wi expressed in terms of the bit weights Wj. j=0, 1, . . . , i−1 corresponding to the bits bj, j=0, 1, . . . , i−1 with lesser significance than the bit bi based at least on said first digital word, wherein the resulting estimated value of the bit weight wi is one of the at least one calibration value. A control unit, a redundant ADC and a computer program are also disclosed.

Abstract translation: 公开了一种确定冗余模数转换器ADC的至少一个校准值的方法。 对于至少第i位bL，对应的位权重wi小于位权重Wj，j = 0,1的总和。 。 。 ，对应于比特bj，j = 0,1，...的i-1。 。 。 ，i-1比位bi的意义不大。 该方法包括对表示比特重量wi的第一电值进行采样; 使用位bj，j = 0,1，进行第一个模数转换，A / D转换。 。 。 ，i-1比位bi具有较小的显着性，以获得所述位bj，j = 0,1的第一数字字。 。 。 i-1，比代表所述第一电值的位bi更不重要; 并且估计以比特权重Wj表示的比特权重Wi的值。 j = 0,1，... 。 。 ，对应于比特bj，j = 0,1，...的i-1。 。 。 ，i-1至少基于所述第一数字字，比所述位bi的重要性低，其中所述位权重wi的所得到的估计值是所述至少一个校准值之一。 还公开了控制单元，冗余ADC和计算机程序。

公开(公告)号：US20110204978A1

公开(公告)日：2011-08-25

申请号：US12993145

申请日：2009-05-25

Applicant: Christer Jansson

Inventor： Christer Jansson

IPC: H03F3/45

CPC classification number: H03F3/45753 ,  H03F2203/45292 ,  H03F2203/45444 ,  H03F2203/45538 ,  H03F2203/45634

Abstract: A comparator circuit (5) comprising a fully differential main amplifier unit (10, 10b). The main amplifier unit (10, 10b) comprises a control port and is adapted to control a bias current of a first branch of the main amplifier unit (10, 10b) and/or a bias current of a second branch of the main amplifier unit (10, 10b) in response to one or more control voltages supplied to the control port of the main amplifier unit (10, 10b). The comparator circuit (5) comprises circuitry (60) for balancing the voltages at the positive and negative input terminals (12a, 12b) of the main amplifier unit (10, 10b) during a first clock phase of the comparator circuit (5). Furthermore, the comparator circuit (10, 10a) comprises a switched-capacitor accumulator unit with a differential input. The switched-capacitor accumulator unit is operatively connected to the positive and negative output terminals (14a, 14b) of the main amplifier unit (10, 10b) for sampling voltages at the positive and negative output terminals (14a, 14b) of the main amplifier unit (10, 10b) during the first clock phase, and operatively connected to the control port of the main amplifier unit (10, 10b) for supplying said one or more control voltages.

Abstract translation: 一种包括全差分主放大器单元（10,10b）的比较器电路（5）。 主放大器单元（10,10b）包括控制端口，并且适于控制主放大器单元（10,10b）的第一支路的偏置电流和/或主放大器单元的第二支路的偏置电流 （10,10b），响应于提供给主放大器单元（10,10b）的控制端口的一个或多个控制电压。 比较器电路（5）包括用于在比较器电路（5）的第一时钟相位期间平衡主放大器单元（10,10b）的正和负输入端（12a，12b）处的电压的电路（60）。 此外，比较器电路（10,10a）包括具有差分输入的开关电容器累加器单元。 开关电容器蓄电单元可操作地连接到主放大器单元（10,10b）的正输出端和负输出端（14a，14b），用于对主放大器的正负输出端（14a，14b）进行采样电压 单元（10,10b），并且可操作地连接到主放大器单元（10,10b）的控制端口，用于提供所述一个或多个控制电压。

公开(公告)号：US20110115538A1

公开(公告)日：2011-05-19

申请号：US12620135

申请日：2009-11-17

Applicant: Christer JANSSON

Inventor： Christer JANSSON

IPC: H03K3/02

CPC classification number: H03K3/35613

Abstract: A latched comparator circuit. The latched comparator circuit comprises a first and a second output terminal (20a, 20b) for outputting a first and a second output voltage, respectively, of the latched comparator circuit (1). Furthermore, the latched comparator circuit comprises a cross-coupled pair of transistors (30a, 30b) operatively connected between the first and the second output terminal (20a, 20b) for providing a positive feedback in the latched comparator circuit (1). In addition, the latched comparator circuit comprises a reset terminal (40) for receiving a reset signal and reset circuitry arranged to balance the first and the second output voltage during a first phase of the reset signal and allow a voltage difference to develop between the first and the second output voltage during a second phase of the reset signal. Moreover, the latched comparator circuit comprises a load unit (55) operatively connected to the cross-coupled pair of transistors and a bias circuit (70) arranged to receive the reset signal and to bias the load unit (55) such that a conductivity of the load unit (55) is higher during the second phase of the reset signal than during the first phase of the reset signal, whereby said positive feedback is stronger during the second phase of the reset signal than during the first phase of the reset signal.

Abstract translation: 锁存比较电路。 锁存比较器电路包括分别用于输出锁存比较器电路（1）的第一和第二输出电压的第一和第二输出端子（20a，20b）。 此外，锁存比较器电路包括可操作地连接在第一和第二输出端子（20a，20b）之间的交叉耦合的一对晶体管（30a，30b），用于在锁存比较器电路（1）中提供正反馈。 此外，锁存比较器电路包括用于接收复位信号的复位端子（40）和复位电路，所述复位电路被布置成在复位信号的第一阶段期间平衡第一和第二输出电压，并允许电压差在第一 以及在复位信号的第二阶段期间的第二输出电压。 此外，锁存比较器电路包括可操作地连接到交叉耦合的晶体管对的负载单元（55）和布置成接收复位信号并偏置负载单元（55）的偏置电路（70），使得电压 在复位信号的第二阶段期间，负载单元（55）比在复位信号的第一阶段期间更高，由此所述正反馈在复位信号的第二阶段期间比在复位信号的第一阶段期间更强。

公开(公告)号：US07902893B1

公开(公告)日：2011-03-08

申请号：US12620149

申请日：2009-11-17

Applicant: Christer Jansson

Inventor： Christer Jansson

IPC: H03K5/12

CPC classification number: H03K5/1565

Abstract: A clock-signal generating unit for generating an output clock signal with a controlled duty cycle based on an input clock signal. The clock-signal generating unit comprises one or more delay lines arranged to generate a plurality of mutually delayed output signals at different positions within the delay line based on the input clock signal. A control unit is arranged to detect a position within one of the delay lines, the output signal of which has a delay, with respect to the input clock signal, that is essentially equal to one period of the input clock signal, and generate an output signal that indicates the detected position. A selection unit is arranged to generate a delayed clock signal that has a delay, with respect to a signal associated with the input clock signal, that is essentially equal to a period of the clock signal multiplied with said duty cycle based on output signals from one of the delay lines and the output signal of the control unit. The clock-signal generating unit comprises circuitry for generating the output clock signal based on the signal associated with the input clock signal and the delayed clock signal. A corresponding method of generating an output clock signal with a controlled duty cycle based on an input clock signal is also disclosed.

Abstract translation: 一种时钟信号产生单元，用于基于输入时钟信号产生具有受控占空比的输出时钟信号。 时钟信号产生单元包括一个或多个延迟线，布置成基于输入时钟信号在延迟线内的不同位置产生多个相互延迟的输出信号。 控制单元被布置成检测相对于输入时钟信号的输出信号具有延迟的一个延迟线内的位置，其基本上等于输入时钟信号的一个周期，并且产生输出 指示检测到的位置的信号。 选择单元被布置成产生相对于与输入时钟信号相关联的信号具有延迟的延迟时钟信号，其基本上等于基于来自一个的输出信号的与所述占空比相乘的时钟信号的周期 的延迟线和控制单元的输出信号。 时钟信号产生单元包括用于基于与输入时钟信号和延迟时钟信号相关联的信号产生输出时钟信号的电路。 还公开了基于输入时钟信号产生具有受控占空比的输出时钟信号的相应方法。

公开(公告)号：US5844514A

公开(公告)日：1998-12-01

申请号：US836525

申请日：1997-04-30

Applicant: Ulf Ringh ,  Christer Jansson

Inventor： Ulf Ringh ,  Christer Jansson

IPC: H03M1/12 ,  H03M1/14 ,  H03M3/02

CPC classification number: H03M3/46 ,  H03M1/145

Abstract: A periodically integrating analog-to-digital converter and a sensor device having such a converter. The analog-to-digital converter has a measured-value-to-pulse-amount converter, i.e., a sigma-delta converter of the first order that is reset to zero before each new period, and a digital counter for the number of feedback signals of known reference value in the measured-value-to-pulse-amount converter. This constitutes a rough measure of the input signal. The analog-to-digital converter also converts the residual value of the measured-value-to-pulse-amount converter at the end of the period to a digital value, and an adder which adds this value to the output signal from the digital counter, resulting in a more accurate measure of the input signal.

Abstract translation: PCT No.PCT / SE95 / 01287第 371日期1997年04月30日 102（e）1997年4月30日PCT PCT 1995年10月31日PCT公布。 WO96 / 13903 PCT出版物 日期1996年5月9日定期整合模数转换器和具有这种转换器的传感器装置。 模数转换器具有测量值到脉冲量的转换器，即，在每个新周期之前复位为零的第一级的Σ-Δ转换器和用于反馈数量的数字计数器 在测量值到脉冲量转换器中已知参考值的信号。 这是输入信号的粗略测量。 模数转换器还将周期结束时的测量值对脉冲量转换器的残余值转换为数字值，以及将该值与来自数字计数器的输出信号相加的加法器 ，从而更准确地测量输入信号。

公开(公告)号：US20110115529A1

公开(公告)日：2011-05-19

申请号：US12620156

申请日：2009-11-17

Applicant: Christer JANSSON

Inventor： Christer JANSSON

IPC: H03K5/22 ,  H03K5/00

CPC classification number: H03K5/2481

Abstract: A latched comparator circuit (1) comprises an input amplification unit (10), a buffer unit (20), and a control unit (30). The input amplification unit (10) comprises a first and a second input terminal (40a, 40b) for receiving a first and a second input voltage, respectively, of the latched comparator circuit (1). The input amplification unit (10) further comprises a first and a second output terminal (50a, 50b) for outputting a first and a second output voltage, respectively, of the input amplification unit (10). In addition, the input amplification unit (10) comprises a reset terminal (60) arranged to receive a reset signal for resetting the input amplification unit. The buffer unit (20) is operatively connected to the first and the second output terminal (50a, 50b) of the input amplification unit (10). Furthermore, the buffer unit (20) comprises a first and a second output terminal (70a, 70b) for outputting a first and a second output voltage, respectively, of the buffer unit (20). The control unit (30) is operatively connected to the input amplification unit (10) and the buffer unit (20). The control unit (30) is adapted to generate the reset signal based on the first and the second output voltage of the buffer unit (20) and a clock signal and to generate an output signal of the latched comparator circuit (1) based on the first and the second output voltage of the buffer unit (20).A method of operating the latched comparator circuit is also disclosed.

Abstract translation: 锁存比较器电路（1）包括输入放大单元（10），缓冲单元（20）和控制单元（30）。 输入放大单元（10）包括分别用于接收锁存比较器电路（1）的第一和第二输入电压的第一和第二输入端子（40a，40b）。 输入放大单元（10）还包括分别输出输入放大单元（10）的第一和第二输出电压的第一和第二输出端子（50a，50b）。 此外，输入放大单元（10）包括复位端（60），其被布置为接收用于复位输入放大单元的复位信号。 缓冲单元（20）可操作地连接到输入放大单元（10）的第一和第二输出端子（50a，50b）。 此外，缓冲单元（20）包括用于分别输出缓冲单元（20）的第一和第二输出电压的第一和第二输出端子（70a，70b）。 控制单元（30）可操作地连接到输入放大单元（10）和缓冲单元（20）。 控制单元（30）适于基于缓冲单元（20）的第一和第二输出电压和时钟信号产生复位信号，并且基于所述锁存比较器电路（1）的输出信号产生 缓冲单元（20）的第一和第二输出电压。 还公开了一种操作锁存比较器电路的方法。

公开(公告)号：US06972701B2

公开(公告)日：2005-12-06

申请号：US10950271

申请日：2004-09-24

Applicant: Christer Jansson

Inventor： Christer Jansson

IPC: H03M1/10 ,  H03M1/36 ,  H03M1/70 ,  H03M1/62 ,  H03M1/84 ,  H03M1/88

CPC classification number: H03M1/1019 ,  H03M1/361 ,  H03M1/70

Abstract: A D/A converter range calibration system in an A/D converter structure including a set of comparators with associated calibrating D/A converters includes means (RCC) for determining the offset error range for the entire set of comparators and means (R-DAC) for adjusting the dynamic range of each calibrating D/A converter to this offset error range.

Abstract translation: 包括具有相关联的校准D / A转换器的一组比较器的A / D转换器结构中的AD / A转换器范围校准系统包括用于确定整个比较器组的偏移误差范围的装置（RCC）和装置（R-DAC） 用于将每个校准D / A转换器的动态范围调整到该偏移误差范围。

公开(公告)号：US06778110B2

公开(公告)日：2004-08-17

申请号：US10668000

申请日：2003-09-22

Applicant: Christer Jansson

Inventor： Christer Jansson

IPC: H03M110

CPC classification number: H03M7/165 ,  H03M1/1004 ,  H03M1/1061 ,  H03M1/167 ,  H03M1/36

Abstract: An A/D converter includes a calibration apparatus handling occurrences of thermometer code bubbles in an A/D sub-converter in at least one A/D converter stage. The calibration apparatus includes means (30) for detecting two A/D sub-converter comparators causing a bubble, means (32, 34, 36) for increasing the threshold of the bubble causing comparator having the lowest threshold by a first predetermined voltage and means (32, 34, 36) for decreasing the threshold of the bubble causing comparator having the highest threshold by a second predetermined voltage.

Abstract translation: A / D转换器包括校准装置，其处理在至少一个A / D转换器级中的A / D子转换器中出现的温度计代码气泡。 校准装置包括用于检测引起气泡的两个A / D子转换器比较器的装置（30），用于将具有最低阈值的气泡引起的比较器的阈值增加第一预定电压的装置（32,34,36） （32,34,36），用于将具有最高阈值的气泡引起的比较器的阈值减小第二预定电压。