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公开(公告)号:US20110115529A1
公开(公告)日:2011-05-19
申请号:US12620156
申请日:2009-11-17
Applicant: Christer JANSSON
Inventor: Christer JANSSON
CPC classification number: H03K5/2481
Abstract: A latched comparator circuit (1) comprises an input amplification unit (10), a buffer unit (20), and a control unit (30). The input amplification unit (10) comprises a first and a second input terminal (40a, 40b) for receiving a first and a second input voltage, respectively, of the latched comparator circuit (1). The input amplification unit (10) further comprises a first and a second output terminal (50a, 50b) for outputting a first and a second output voltage, respectively, of the input amplification unit (10). In addition, the input amplification unit (10) comprises a reset terminal (60) arranged to receive a reset signal for resetting the input amplification unit. The buffer unit (20) is operatively connected to the first and the second output terminal (50a, 50b) of the input amplification unit (10). Furthermore, the buffer unit (20) comprises a first and a second output terminal (70a, 70b) for outputting a first and a second output voltage, respectively, of the buffer unit (20). The control unit (30) is operatively connected to the input amplification unit (10) and the buffer unit (20). The control unit (30) is adapted to generate the reset signal based on the first and the second output voltage of the buffer unit (20) and a clock signal and to generate an output signal of the latched comparator circuit (1) based on the first and the second output voltage of the buffer unit (20).A method of operating the latched comparator circuit is also disclosed.
Abstract translation: 锁存比较器电路(1)包括输入放大单元(10),缓冲单元(20)和控制单元(30)。 输入放大单元(10)包括分别用于接收锁存比较器电路(1)的第一和第二输入电压的第一和第二输入端子(40a,40b)。 输入放大单元(10)还包括分别输出输入放大单元(10)的第一和第二输出电压的第一和第二输出端子(50a,50b)。 此外,输入放大单元(10)包括复位端(60),其被布置为接收用于复位输入放大单元的复位信号。 缓冲单元(20)可操作地连接到输入放大单元(10)的第一和第二输出端子(50a,50b)。 此外,缓冲单元(20)包括用于分别输出缓冲单元(20)的第一和第二输出电压的第一和第二输出端子(70a,70b)。 控制单元(30)可操作地连接到输入放大单元(10)和缓冲单元(20)。 控制单元(30)适于基于缓冲单元(20)的第一和第二输出电压和时钟信号产生复位信号,并且基于所述锁存比较器电路(1)的输出信号产生 缓冲单元(20)的第一和第二输出电压。 还公开了一种操作锁存比较器电路的方法。
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公开(公告)号:US20110115538A1
公开(公告)日:2011-05-19
申请号:US12620135
申请日:2009-11-17
Applicant: Christer JANSSON
Inventor: Christer JANSSON
IPC: H03K3/02
CPC classification number: H03K3/35613
Abstract: A latched comparator circuit. The latched comparator circuit comprises a first and a second output terminal (20a, 20b) for outputting a first and a second output voltage, respectively, of the latched comparator circuit (1). Furthermore, the latched comparator circuit comprises a cross-coupled pair of transistors (30a, 30b) operatively connected between the first and the second output terminal (20a, 20b) for providing a positive feedback in the latched comparator circuit (1). In addition, the latched comparator circuit comprises a reset terminal (40) for receiving a reset signal and reset circuitry arranged to balance the first and the second output voltage during a first phase of the reset signal and allow a voltage difference to develop between the first and the second output voltage during a second phase of the reset signal. Moreover, the latched comparator circuit comprises a load unit (55) operatively connected to the cross-coupled pair of transistors and a bias circuit (70) arranged to receive the reset signal and to bias the load unit (55) such that a conductivity of the load unit (55) is higher during the second phase of the reset signal than during the first phase of the reset signal, whereby said positive feedback is stronger during the second phase of the reset signal than during the first phase of the reset signal.
Abstract translation: 锁存比较电路。 锁存比较器电路包括分别用于输出锁存比较器电路(1)的第一和第二输出电压的第一和第二输出端子(20a,20b)。 此外,锁存比较器电路包括可操作地连接在第一和第二输出端子(20a,20b)之间的交叉耦合的一对晶体管(30a,30b),用于在锁存比较器电路(1)中提供正反馈。 此外,锁存比较器电路包括用于接收复位信号的复位端子(40)和复位电路,所述复位电路被布置成在复位信号的第一阶段期间平衡第一和第二输出电压,并允许电压差在第一 以及在复位信号的第二阶段期间的第二输出电压。 此外,锁存比较器电路包括可操作地连接到交叉耦合的晶体管对的负载单元(55)和布置成接收复位信号并偏置负载单元(55)的偏置电路(70),使得电压 在复位信号的第二阶段期间,负载单元(55)比在复位信号的第一阶段期间更高,由此所述正反馈在复位信号的第二阶段期间比在复位信号的第一阶段期间更强。
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