Semiconductor package structure and method for preparing the same

    公开(公告)号:US11876063B2

    公开(公告)日:2024-01-16

    申请号:US17462330

    申请日:2021-08-31

    发明人: Shing-Yih Shih

    IPC分类号: H01L23/00

    摘要: A semiconductor package structure includes a first semiconductor wafer including a first bonding pad. The semiconductor package structure also includes a second semiconductor wafer including a second bonding pad and a third bonding pad. The second bonding pad and the third bonding pad are bonded to the first bonding pad of the first semiconductor wafer. The semiconductor package structure further includes a first via penetrating through the second semiconductor wafer to physically contact the first bonding pad of the first semiconductor wafer. A portion of the first via is disposed between the second bonding pad and the third bonding pad.

    SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR PREPARING THE SAME

    公开(公告)号:US20240047394A1

    公开(公告)日:2024-02-08

    申请号:US18381911

    申请日:2023-10-19

    发明人: SHING-YIH SHIH

    IPC分类号: H01L23/00

    摘要: A semiconductor package structure includes a first semiconductor wafer including a first bonding pad. The semiconductor package structure also includes a second semiconductor wafer including a second bonding pad and a third bonding pad. The second bonding pad and the third bonding pad are bonded to the first bonding pad of the first semiconductor wafer. The semiconductor package structure further includes a first via penetrating through the second semiconductor wafer to physically contact the first bonding pad of the first semiconductor wafer. A portion of the first via is disposed between the second bonding pad and the third bonding pad.

    Semiconductor packages
    6.
    发明授权

    公开(公告)号:US11764121B2

    公开(公告)日:2023-09-19

    申请号:US17929871

    申请日:2022-09-06

    发明人: Keun-ho Choi

    IPC分类号: H01L23/31 H01L23/00

    摘要: Provided is a stacked semiconductor package including a package base substrate including a plurality of signal wires and at least one power wire, wherein a plurality of top surface connecting pads and a plurality of bottom surface connecting pads are on a top surface and a bottom surface of the package base substrate, respectively; and a plurality of semiconductor chips that are sequentially stacked on the package base substrate and are electrically connected to the top surface connecting pads, the plurality of semiconductor chips including a first semiconductor chip that is a bottommost semiconductor chip, and a second semiconductor chip that is on the first semiconductor chip, wherein the signal wires are arranged apart from a portion of the package base substrate, the first portion that overlaps a first edge of the first semiconductor chip, the first edge overlapping the second semiconductor chip in a vertical direction.