公开(公告)号：US12205912B2

公开(公告)日：2025-01-21

申请号：US18381911

申请日：2023-10-19

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih

IPC: H01L23/00

Abstract: A semiconductor package structure includes a first semiconductor wafer including a first bonding pad. The semiconductor package structure also includes a second semiconductor wafer including a second bonding pad and a third bonding pad. The second bonding pad and the third bonding pad are bonded to the first bonding pad of the first semiconductor wafer. The semiconductor package structure further includes a first via penetrating through the second semiconductor wafer to physically contact the first bonding pad of the first semiconductor wafer. A portion of the first via is disposed between the second bonding pad and the third bonding pad.

公开(公告)号：US11502038B2

公开(公告)日：2022-11-15

申请号：US16983533

申请日：2020-08-03

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih

IPC: H01L23/538 ,  H01L21/768

Abstract: The present disclosure provides a semiconductor structure having a first wafer including a first substrate, a first dielectric layer over the first substrate, and a first conductive pad surrounded by the first dielectric layer; a second wafer including a second dielectric layer, a second substrate over the second dielectric layer, and a second conductive pad surrounded by the second dielectric layer; a bonding dielectric disposed between the first dielectric layer and the second dielectric layer to bond the first dielectric layer with the second dielectric layer; and a conductive via extending from the first conductive pad and surrounded by the bonding dielectric, the second conductive pad and the second wafer.

公开(公告)号：US11469173B2

公开(公告)日：2022-10-11

申请号：US17157358

申请日：2021-01-25

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/528

Abstract: The present disclosure relates to a method of manufacturing a semiconductor structure. The method of manufacturing a semiconductor structure includes providing a carrier; disposing a dielectric layer over the carrier; removing a first portion of the dielectric layer to form an opening extending through the dielectric layer; removing a second portion of the dielectric layer to form a trench extending through and along the dielectric layer; disposing a conductive material into the opening and the trench to form a conductive via and a metallic strip, respectively; removing a third portion of the dielectric layer; detaching the dielectric layer from the carrier; disposing the dielectric layer over a substrate; disposing a die over the substrate; and forming a molding to surround the die.

公开(公告)号：US11450556B2

公开(公告)日：2022-09-20

申请号：US17019343

申请日：2020-09-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih ,  Chih-Ching Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/311 ,  H01L23/528

Abstract: A semiconductor structure includes a semiconductor device, an interconnect structure, a dielectric layer, and a redistribution layer (RDL). The interconnect structure is disposed over the semiconductor device. The dielectric layer is disposed over the interconnect structure. The RDL includes a conductive structure over the dielectric layer and a conductive via extending downwards from the conductive structure and through the dielectric layer. The conductive via includes a bottom portion, a top portion and a tapered portion between the bottom and top portions, in which the tapered portion has a width variation greater than that of the bottom and top portions.

公开(公告)号：US11355464B2

公开(公告)日：2022-06-07

申请号：US17093974

申请日：2020-11-10

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih ,  Tse-Yao Huang

IPC: H01L23/00

Abstract: A semiconductor device structure includes a silicon layer disposed over a first semiconductor die, and a first mask layer disposed over the silicon layer. The semiconductor device structure also includes a second semiconductor die disposed over the first mask layer, and a through silicon via penetrating through the silicon layer and the first mask layer. A bottom surface of the through silicon via is greater than a top surface of the through silicon via, and the top surface of the through silicon via is greater than a cross-section of the through silicon via between and parallel to the top surface and the bottom surface of the through silicon via.

公开(公告)号：US11315904B2

公开(公告)日：2022-04-26

申请号：US16875660

申请日：2020-05-15

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00

Abstract: A semiconductor assembly comprises a first device, a second device, a passivation layer and an interconnect structure. The first device comprises a first top metal layer. The second device comprises a second bottom metal layer. The passivation layer is disposed on the second device. The interconnect structure electrically couples the first device to the second device, wherein the interconnect structure comprises a head member, a first leg and a second leg. The head member is disposed on the passivation layer. The first leg penetrates through the passivation layer and the second device, wherein the first leg connects the head member to the first top metal layer. The second leg penetrates through the passivation layer and extends into the second device to connect the head member to the second bottom metal layer. The first leg and the second leg comprise a top portion, an intermediate portion and a bottom portion.

公开(公告)号：US11309254B2

公开(公告)日：2022-04-19

申请号：US16793069

申请日：2020-02-18

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes a substrate, a conductive feature, a redistribution layer, at least one through silicon via and at least one bump. The conductive feature is disposed over a front surface of the substrate, and the redistribution layer is disposed over a back surface opposite to the front surface. The through silicon via penetrates through the substrate and contacts the conductive feature embedded in an insulative layer. The bump contacts the redistribution layer and the through silicon via and serves as an electrical connection therebetween.

公开(公告)号：US11302608B2

公开(公告)日：2022-04-12

申请号：US16908022

申请日：2020-06-22

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tse-Yao Huang ,  Shing-Yih Shih

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/00 ,  H01L21/768

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first die, a first conductive feature positioned in the first die, a second die positioned on the first die, a first mask layer positioned on the second die, a second mask layer positioned on the first mask layer, a conductive filler layer positioned penetrating the second mask layer, the first mask layer, and the second die, extending to the first die, and contacting the first conductive feature, isolation layers positioned between the conductive filler layer and the first die, between the conductive filler layer and the second die, and between the conductive filler layer and the first mask layer, and protection layers positioned between the conductive filler layer and the second mask layer and between the conductive filler layer and the first mask layer, and covering upper portions of the isolation layers.

公开(公告)号：US11189523B2

公开(公告)日：2021-11-30

申请号：US16439690

申请日：2019-06-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih ,  Mao-Ying Wang ,  Hung-Mo Wu

IPC: H01L21/768 ,  H01L23/31 ,  H01L23/522

Abstract: A method of forming a semiconductor structure includes the following steps. A dielectric layer is formed over a conductive line. A photoresist layer is formed over the dielectric layer. The photoresist layer is patterned to form a mask feature and an opening is defined by the mask feature. The opening has a bottom portion and a top portion communicated to the bottom portion, and the top portion is wider than the bottom portion. The dielectric layer is etched to form a via hole in the dielectric layer using the mask feature as an etch mask, such that the via hole has a bottom portion and a tapered portion over the bottom portion. The conductive material is filled in the via hole to form a conductive via.

公开(公告)号：US11133251B1

公开(公告)日：2021-09-28

申请号：US16819758

申请日：2020-03-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih

IPC: H01L23/528 ,  H01L23/538 ,  H01L23/28

Abstract: The present disclosure provides a semiconductor assembly and method of manufacturing the same. The semiconductor assembly includes a semiconductor device, a bulk semiconductor, a passivation layer, at least one conductive plug, a plurality of protective liners, and a plurality of isolation liners. The bulk semiconductor is disposed over the semiconductor device. The passivation layer covers the bulk semiconductor. The conductive plug comprises a first block disposed in the passivation layer and a second block disposed between the first block and the conductive pad, wherein portions of peripheries of the first and second blocks of the conductive plug are surrounded by the protective liners and the isolation liners.