公开(公告)号：US11942277B2

公开(公告)日：2024-03-26

申请号：US17228729

申请日：2021-04-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Mao-Ying Wang ,  Yu-Ting Lin

IPC: H01G4/30 ,  H01G4/012 ,  H01G4/33 ,  H01L49/02

CPC classification number: H01G4/30 ,  H01G4/012 ,  H01G4/33 ,  H01L28/60 ,  H01L28/92

Abstract: A method of manufacturing a semiconductor structure includes: forming a first oxide layer over a landing pad layer; forming a middle patterned dielectric layer over the first oxide layer; sequentially forming a second oxide layer and a top dielectric layer over the middle patterned dielectric layer; forming a trench through the top dielectric layer, the second oxide layer and the first oxide layer; conformally forming a bottom conductive layer in the trench; removing a portion of the top dielectric layer adjacent to the trench to expose a portion of the second oxide layer beneath the portion of the top dielectric layer; and performing an etching process to remove the second oxide layer and the first oxide layer. A semiconductor structure is also provided.

公开(公告)号：US11309316B1

公开(公告)日：2022-04-19

申请号：US17074873

申请日：2020-10-20

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hui-Lin Chen ,  Mao-Ying Wang ,  Yu-Ting Lin ,  Lai-Cheng Tien

IPC: H01L27/108

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The method for fabricating the semiconductor device includes providing a substrate including an array area and a peripheral area adjacent to the array area, forming word line structures and source/drain regions in the array area, and a word line protection layer on the array area, forming a first hard mask layer over the substrate and having a step height adjacent to a border between the array area and the peripheral area, forming a bit line contact in the array area and between the word line structures by using the first hard mask layer as a pattern guide, and forming a gate electrode layer on the peripheral area.

公开(公告)号：US12230450B2

公开(公告)日：2025-02-18

申请号：US18444758

申请日：2024-02-18

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Mao-Ying Wang ,  Yu-Ting Lin

IPC: H01G4/33 ,  H01G4/012 ,  H01G4/30 ,  H01L49/02

Abstract: A method of manufacturing a semiconductor structure includes: forming a first oxide layer over a landing pad layer; forming a middle patterned dielectric layer over the first oxide layer; sequentially forming a second oxide layer and a top dielectric layer over the middle patterned dielectric layer; forming a trench through the top dielectric layer, the second oxide layer and the first oxide layer; conformally forming a bottom conductive layer in the trench; removing a portion of the top dielectric layer adjacent to the trench to expose a portion of the second oxide layer beneath the portion of the top dielectric layer; and performing an etching process to remove the second oxide layer and the first oxide layer. A semiconductor structure is also provided.

公开(公告)号：US11437383B1

公开(公告)日：2022-09-06

申请号：US17337061

申请日：2021-06-02

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Mao-Ying Wang ,  Yu-Ting Lin

IPC: H01L21/00 ,  H01L27/108 ,  H01L49/02

Abstract: The present disclosure provides a method for fabricating DRAM devices with cylinder-type stacked capacitors. By utilizing offsetting of a first lattice pattern on a second silicon nitride layer (i.e., a middle silicon nitride layer) and a second lattice pattern on a third silicon nitride layer (i.e., a top silicon nitride layer), a collapse or deformation phenomenon of bottom electrodes of stacked capacitors can be reduced or eliminated. The wobbling phenomenon of bottom electrodes of stacked capacitors can be significantly reduced.

公开(公告)号：US11189523B2

公开(公告)日：2021-11-30

申请号：US16439690

申请日：2019-06-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih ,  Mao-Ying Wang ,  Hung-Mo Wu

IPC: H01L21/768 ,  H01L23/31 ,  H01L23/522

Abstract: A method of forming a semiconductor structure includes the following steps. A dielectric layer is formed over a conductive line. A photoresist layer is formed over the dielectric layer. The photoresist layer is patterned to form a mask feature and an opening is defined by the mask feature. The opening has a bottom portion and a top portion communicated to the bottom portion, and the top portion is wider than the bottom portion. The dielectric layer is etched to form a via hole in the dielectric layer using the mask feature as an etch mask, such that the via hole has a bottom portion and a tapered portion over the bottom portion. The conductive material is filled in the via hole to form a conductive via.

公开(公告)号：US11063011B1

公开(公告)日：2021-07-13

申请号：US16796904

申请日：2020-02-20

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chia-Lin Tsai ,  Mao-Ying Wang

IPC: H01L23/00

Abstract: A chip includes pads having first connecting surfaces, and conductive structures located on the first connecting surfaces. The conductive structures are disposed on the first connecting surfaces. Each of the conductive structures includes first metal layer, second metal layer, and third metal layer. The first metal layer connects one of the pads, and the second metal layer is disposed between the first metal layer and the third metal layer. On every pad, the first metal layer, the second metal layer, and the third metal layer are stacked along first direction on the first connecting surface of the pad, and the first direction is parallel to normal direction of the first connecting surface, and the first metal layer is made of material comprising gold, and the second metal layer is made of material comprising nickel. A wafer is also provided.

公开(公告)号：US10573602B2

公开(公告)日：2020-02-25

申请号：US16015559

申请日：2018-06-22

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Mao-Ying Wang ,  Pei-Lin Huang

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/522

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first die and a conductive layer. The first die is to be bonded with, in a direction, a second die external to the semiconductor device. The conductive layer, between the first die and the second die in the direction, has a reference ground.

公开(公告)号：US11621318B2

公开(公告)日：2023-04-04

申请号：US17358195

申请日：2021-06-25

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Mao-Ying Wang ,  Tse-Yao Huang

IPC: H01L27/105 ,  H01L49/02 ,  H01L27/108

Abstract: The present disclosure provides a capacitor, a semiconductor device, and a method for preparing a capacitor. The semiconductor device includes a plurality of memory cells, at least one of the memory cells including a capacitor. The capacitor includes a first electrode comprising titanium nitride and disposed on a substrate, a dielectric film disposed on the first electrode, a multilayer film disposed on the dielectric film, and a second electrode comprising titanium nitride and disposed on the multilayer film. The method for preparing the capacitor includes forming the first electrode comprising titanium nitride on the substrate, forming a dielectric film on the first electrode, forming the multilayer film on the dielectric film, and forming the second electrode comprising titanium nitride on the multilayer film.

公开(公告)号：US11588011B2

公开(公告)日：2023-02-21

申请号：US17808301

申请日：2022-06-22

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Lai-Cheng Tien ,  Wei-Chuan Fang ,  Yu-Ting Lin ,  Mao-Ying Wang

IPC: H01L49/02 ,  H01G4/30 ,  H01G4/232 ,  H01G4/005

Abstract: A method of capacitance structure manufacturing includes following operations. A plurality of insulating tubes is formed over a substrate and perpendicular to the substrate. A first supporting layer and a second supporting layer above the first supporting layer are formed and connect the insulating tubes. The first supporting layer protrudes from the second supporting layer. Conductive material is filled in the insulating tubes to form rod capacitors forming a capacitor array and the capacitor array is covered by an oxide layer from its top to the substrate. The oxide layer is formed along the first supporting layer and the second supporting layer such that the oxide layer extends along a direction having an angle with respect to the substrate.

公开(公告)号：US11683928B2

公开(公告)日：2023-06-20

申请号：US17538068

申请日：2021-11-30

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hui-Lin Chen ,  Mao-Ying Wang ,  Yu-Ting Lin ,  Lai-Cheng Tien

IPC: H10B12/00

CPC classification number: H10B12/09 ,  H10B12/053 ,  H10B12/34 ,  H10B12/485 ,  H10B12/50

Abstract: The present application discloses a semiconductor device. The semiconductor device includes a substrate comprising an array area and a peripheral area adjacent to the array area; word line structures positioned in the array area; a word line hard mask layer positioned on the array area; a word line protection layer positioned on the word line hard mask layer; a gate electrode layer positioned on the peripheral area and separated from the word line hard mask layer and the word line protection layer; a peripheral protection layer positioned on the to gate electrode layer; and a first hard mask layer positioned over the array area and the peripheral area. A horizontal distance between the word line protection layer and the gate electrode layer is greater than or equal to three times of a thickness of the first hard mask layer.