Invention Grant
- Patent Title: Method for fabricating dynamic random access memory devices
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Application No.: US17337061Application Date: 2021-06-02
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Publication No.: US11437383B1Publication Date: 2022-09-06
- Inventor: Mao-Ying Wang , Yu-Ting Lin
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L27/108 ; H01L49/02

Abstract:
The present disclosure provides a method for fabricating DRAM devices with cylinder-type stacked capacitors. By utilizing offsetting of a first lattice pattern on a second silicon nitride layer (i.e., a middle silicon nitride layer) and a second lattice pattern on a third silicon nitride layer (i.e., a top silicon nitride layer), a collapse or deformation phenomenon of bottom electrodes of stacked capacitors can be reduced or eliminated. The wobbling phenomenon of bottom electrodes of stacked capacitors can be significantly reduced.
Information query
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