公开(公告)号：US09659886B2

公开(公告)日：2017-05-23

申请号：US15193117

申请日：2016-06-27

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chung-Hsin Lin ,  Ping-Heng Wu ,  Chao-Wen Lay ,  Hung-Mo Wu ,  Ying-Cheng Chuang

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/52 ,  H01L21/4763 ,  H01L23/48 ,  H01L23/00 ,  H01L23/522 ,  H01L23/31 ,  H01L23/525

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/525 ,  H01L23/562 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/0345 ,  H01L2224/036 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/04953 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.

公开(公告)号：US20160307859A1

公开(公告)日：2016-10-20

申请号：US15193117

申请日：2016-06-27

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chung-Hsin Lin ,  Ping-Heng Wu ,  Chao-Wen Lay ,  Hung-Mo Wu ,  Ying-Cheng Chuang

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/525 ,  H01L23/562 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/0345 ,  H01L2224/036 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/04953 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.

Abstract translation: 本发明提供一种半导体器件，其包括衬底，电介质层，虚拟焊盘，焊盘，再分配层和金属互连。 衬底包括非器件区域和器件区域。 介电层位于非器件区域和器件区域上。 虚拟焊盘位于非器件区的介质层上。 金属互连在非器件区的介质层中并连接到虚拟焊盘。 焊盘位于器件区域的介电层上。 缓冲层位于接合焊盘和电介质层之间。 缓冲层包括金属，金属氮化物或其组合。 再分布层在电介质层上并连接虚拟焊盘和焊盘。

公开(公告)号：US11189523B2

公开(公告)日：2021-11-30

申请号：US16439690

申请日：2019-06-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih ,  Mao-Ying Wang ,  Hung-Mo Wu

IPC: H01L21/768 ,  H01L23/31 ,  H01L23/522

Abstract: A method of forming a semiconductor structure includes the following steps. A dielectric layer is formed over a conductive line. A photoresist layer is formed over the dielectric layer. The photoresist layer is patterned to form a mask feature and an opening is defined by the mask feature. The opening has a bottom portion and a top portion communicated to the bottom portion, and the top portion is wider than the bottom portion. The dielectric layer is etched to form a via hole in the dielectric layer using the mask feature as an etch mask, such that the via hole has a bottom portion and a tapered portion over the bottom portion. The conductive material is filled in the via hole to form a conductive via.

公开(公告)号：US20150076698A1

公开(公告)日：2015-03-19

申请号：US14028554

申请日：2013-09-17

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chung-Hsin Lin ,  Ping-Heng Wu ,  Chao-Wen Lay ,  Hung-Mo Wu ,  Ying-Cheng Chuang

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/525 ,  H01L23/562 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/0345 ,  H01L2224/036 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/04953 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.

Abstract translation: 本发明提供一种半导体器件，其包括衬底，电介质层，虚拟焊盘，焊盘，再分配层和金属互连。 衬底包括非器件区域和器件区域。 介电层位于非器件区域和器件区域上。 虚拟焊盘位于非器件区的介质层上。 金属互连在非器件区的介质层中并连接到虚拟焊盘。 焊盘位于器件区域的介电层上。 缓冲层位于接合焊盘和电介质层之间。 缓冲层包括金属，金属氮化物或其组合。再分配层在电介质层上并连接虚拟焊盘和焊盘。

公开(公告)号：US20220028734A1

公开(公告)日：2022-01-27

申请号：US17449951

申请日：2021-10-05

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih ,  Mao-Ying Wang ,  Hung-Mo Wu

IPC: H01L21/768 ,  H01L23/31 ,  H01L23/522

Abstract: A semiconductor structure includes a semiconductor device, a conductive line, a dielectric layer and a redistribution layer (RDL). The conductive line is present over the semiconductor device. The dielectric layer is present over the conductive line. The RDL includes a conductive structure over the dielectric layer and a conductive via extending downwards from the conductive structure and through the dielectric layer. The conductive via comprises a bottom portion, a top portion, and a tapered portion between the bottom and top portions, wherein the tapered portion has a width variation greater than that of the bottom and top portions.

公开(公告)号：US09418949B2

公开(公告)日：2016-08-16

申请号：US14028554

申请日：2013-09-17

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chung-Hsin Lin ,  Ping-Heng Wu ,  Chao-Wen Lay ,  Hung-Mo Wu ,  Ying-Cheng Chuang

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/52 ,  H01L21/4763 ,  H01L23/48 ,  H01L23/00 ,  H01L23/522 ,  H01L23/31 ,  H01L23/525

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/525 ,  H01L23/562 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/0345 ,  H01L2224/036 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/04953 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.

Abstract translation: 本发明提供一种半导体器件，其包括衬底，电介质层，虚拟焊盘，焊盘，再分配层和金属互连。 衬底包括非器件区域和器件区域。 介电层位于非器件区域和器件区域上。 虚拟焊盘位于非器件区的介质层上。 金属互连在非器件区的介质层中并连接到虚拟焊盘。 焊盘位于器件区域的介电层上。 缓冲层位于接合焊盘和电介质层之间。 缓冲层包括金属，金属氮化物或其组合。 再分布层在电介质层上并连接虚拟焊盘和焊盘。