Wafer test system and methods thereof

    公开(公告)号:US11486899B2

    公开(公告)日:2022-11-01

    申请号:US16778746

    申请日:2020-01-31

    Abstract: A wafer test system includes a probe apparatus, a data server, an automation subsystem, and a probe mark assessment subsystem. The probe apparatus includes a probe card, a tester, and a camera. The probe card includes probe pins for contacting test pads in the wafer, and the camera captures an image of the test pads. The automation subsystem obtains an image specification from the probe apparatus and triggers an automated assessment of a probe mark in the image of the test pads. The probe mark assessment subsystem performs the automated assessment of the probe mark in the image of the test pads. The probe mark assessment subsystem performs an image-processing operation to obtain a probe mark assessment result, and the automation subsystem stops the probe apparatus if the probe mark assessment result indicates a probe test failure.

    Wafer inspection system
    2.
    发明授权

    公开(公告)号:US12148144B2

    公开(公告)日:2024-11-19

    申请号:US17723723

    申请日:2022-04-19

    Abstract: A wafer inspection system is provided. The wafer inspection system includes a memory unit configured to store an image of a device under test (DUT) on a wafer, an image-uploading unit configured to upload the image to a processing unit, and a processing unit. The processing unit is configured to identify a plurality of candidate regions on the image; generate a confidence score for each of the plurality of candidate regions, wherein the confidence score indicates a probability of a candidate region including a probe mark; select a first candidate region having the highest confidence score as a selected region; determine whether a second candidate region in the plurality of candidate regions includes the same probe mark as the first candidate region; and eliminate the second candidate region if the second candidate region includes the same probe mark as the first candidate region.

    Chip and wafer having multi-layered pad

    公开(公告)号:US11063011B1

    公开(公告)日:2021-07-13

    申请号:US16796904

    申请日:2020-02-20

    Abstract: A chip includes pads having first connecting surfaces, and conductive structures located on the first connecting surfaces. The conductive structures are disposed on the first connecting surfaces. Each of the conductive structures includes first metal layer, second metal layer, and third metal layer. The first metal layer connects one of the pads, and the second metal layer is disposed between the first metal layer and the third metal layer. On every pad, the first metal layer, the second metal layer, and the third metal layer are stacked along first direction on the first connecting surface of the pad, and the first direction is parallel to normal direction of the first connecting surface, and the first metal layer is made of material comprising gold, and the second metal layer is made of material comprising nickel. A wafer is also provided.

    Wafer inspection system method
    4.
    发明授权

    公开(公告)号:US12211200B2

    公开(公告)日:2025-01-28

    申请号:US17724154

    申请日:2022-04-19

    Abstract: A wafer inspection method is provided. The wafer inspection method includes identifying a plurality of candidate regions on an image of a DUT on a wafer; generating a confidence score for each of the plurality of candidate regions, wherein the confidence score indicates a probability of a candidate region including a probe mark; selecting a first candidate region having the highest confidence score as a selected region; determining whether a second candidate region in the plurality of candidate regions includes the same probe mark as the first candidate region; and eliminating the second candidate region if the second candidate region includes the same probe mark as the first candidate region.

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