公开(公告)号：US11309316B1

公开(公告)日：2022-04-19

申请号：US17074873

申请日：2020-10-20

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hui-Lin Chen ,  Mao-Ying Wang ,  Yu-Ting Lin ,  Lai-Cheng Tien

IPC: H01L27/108

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The method for fabricating the semiconductor device includes providing a substrate including an array area and a peripheral area adjacent to the array area, forming word line structures and source/drain regions in the array area, and a word line protection layer on the array area, forming a first hard mask layer over the substrate and having a step height adjacent to a border between the array area and the peripheral area, forming a bit line contact in the array area and between the word line structures by using the first hard mask layer as a pattern guide, and forming a gate electrode layer on the peripheral area.

公开(公告)号：US11683928B2

公开(公告)日：2023-06-20

申请号：US17538068

申请日：2021-11-30

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hui-Lin Chen ,  Mao-Ying Wang ,  Yu-Ting Lin ,  Lai-Cheng Tien

IPC: H10B12/00

CPC classification number: H10B12/09 ,  H10B12/053 ,  H10B12/34 ,  H10B12/485 ,  H10B12/50

Abstract: The present application discloses a semiconductor device. The semiconductor device includes a substrate comprising an array area and a peripheral area adjacent to the array area; word line structures positioned in the array area; a word line hard mask layer positioned on the array area; a word line protection layer positioned on the word line hard mask layer; a gate electrode layer positioned on the peripheral area and separated from the word line hard mask layer and the word line protection layer; a peripheral protection layer positioned on the to gate electrode layer; and a first hard mask layer positioned over the array area and the peripheral area. A horizontal distance between the word line protection layer and the gate electrode layer is greater than or equal to three times of a thickness of the first hard mask layer.

公开(公告)号：US11588011B2

公开(公告)日：2023-02-21

申请号：US17808301

申请日：2022-06-22

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Lai-Cheng Tien ,  Wei-Chuan Fang ,  Yu-Ting Lin ,  Mao-Ying Wang

IPC: H01L49/02 ,  H01G4/30 ,  H01G4/232 ,  H01G4/005

Abstract: A method of capacitance structure manufacturing includes following operations. A plurality of insulating tubes is formed over a substrate and perpendicular to the substrate. A first supporting layer and a second supporting layer above the first supporting layer are formed and connect the insulating tubes. The first supporting layer protrudes from the second supporting layer. Conductive material is filled in the insulating tubes to form rod capacitors forming a capacitor array and the capacitor array is covered by an oxide layer from its top to the substrate. The oxide layer is formed along the first supporting layer and the second supporting layer such that the oxide layer extends along a direction having an angle with respect to the substrate.

公开(公告)号：US11450553B2

公开(公告)日：2022-09-20

申请号：US16993251

申请日：2020-08-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Lai-Cheng Tien ,  Chih-Lin Huang ,  Zhi-Yi Huang ,  Hsu Chiang

IPC: H01L21/762 ,  H01L23/00

Abstract: A method of forming a semiconductor structure includes following steps. A semiconductor material structure is formed over a substrate. A first pad layer is formed over the semiconductor material structure. The first pad layer and the semiconductor material structure are etched to form a trench. An oxidation process is performed on a sidewall of the semiconductor material structure to form a first oxide structure on the sidewall of the semiconductor material structure. A second oxide structure is formed in the trench.