公开(公告)号：US12093190B2

公开(公告)日：2024-09-17

申请号：US17768101

申请日：2020-11-05

Applicant: NEC Corporation

Inventor： Yuki Ashino ,  Kazushi Sugyo

IPC: G06F12/14 ,  G06F16/174 ,  H04L69/04

CPC classification number: G06F12/14 ,  H04L69/04 ,  G06F16/1744 ,  G06F2212/1052 ,  G06F2212/154 ,  G11C2207/102

Abstract: In order to record communication data via a communication network, in a storage apparatus in accordance with an appropriate data recording method, a data processing apparatus includes: an obtaining unit configured to obtain communication data including one or more packets continuously communicated via a communication network; a recording unit configured to record the communication data in a storage; and a reading processing unit configured to read the communication data from the storage, wherein the recording unit selects a first data compression method from among a plurality of data compression methods based on compression rate for each data compression method, reading speed of the communication data from the storage, and decompression speed of the communication data required from reading of the communication data to decompression of the communication data in accordance with each compression method, and records the communication data in accordance with the first data compression method.

公开(公告)号：US20170255394A1

公开(公告)日：2017-09-07

申请号：US15448327

申请日：2017-03-02

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Michael Hawjing Lo

IPC: G06F3/06 ,  G06F13/42 ,  G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G06F12/06 ,  G06F13/1668 ,  G06F13/1673 ,  G06F13/4234 ,  G11C7/1006 ,  G11C2207/102 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Power saving techniques for memory systems are disclosed. In particular, exemplary aspects of the present disclosure contemplate taking advantage of patterns that may exist within memory elements and eliminating duplicative data transfers. Specifically, if data is repetitive, instead of sending the same data repeatedly, the data may be sent only a single time with instructions that cause the data to be replicated at a receiving end to restore the data to its original repeated state. By reducing the amount of data that is transferred between a host and a memory element, power consumption is reduced.

公开(公告)号：US09606870B1

公开(公告)日：2017-03-28

申请号：US14230405

申请日：2014-03-31

Applicant: EMC Corporation

Inventor： David Meiri ,  Anton Kucherov ,  Vladimir Shveidel

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F3/0638 ,  G06F3/0608 ,  G06F3/0619 ,  G06F3/0661 ,  G06F3/0688 ,  G06F11/1068 ,  G06F11/108 ,  G06F11/1092 ,  G06F11/2069 ,  G06F2201/85 ,  G06F2211/1014 ,  G11C29/52 ,  G11C2207/102

Abstract: In one aspect, a method includes splitting empty RAID stripes into sub-stripes and storing pages into the sub-stripes based on a compressibility score. In another aspect, a method includes reading pages from 1-stripes, storing compressed data in a temporary location, reading multiple stripes, determining compressibility score for each stripe and filling stripes based on the compressibility score. In a further aspect, a method includes scanning a dirty queue in a system cache, compressing pages ready for destaging, combining compressed pages in to one aggregated page, writing one aggregated page to one stripe and storing pages with same compressibility score in a stripe.

公开(公告)号：US20090243652A1

公开(公告)日：2009-10-01

申请号：US12480213

申请日：2009-06-08

Applicant: Nij Dorairaj ,  Raminda Madurawe

Inventor： Nij Dorairaj ,  Raminda Madurawe

IPC: H03K19/173 ,  G06F7/50

CPC classification number: H03K19/17728 ,  G11C7/1006 ,  G11C11/419 ,  G11C2207/102

Abstract: A computational unit is disclosed to increment or decrement n-bits of data. The unit has n/3 logic blocks to process the n-bits of data, each logic block including: first and second multiplexers to propagate a carry chain; and first, second and third exclusive—OR (XOR) circuits coupled to the carry chain of the multiplexers to generate a 3-bit incremented output.

Abstract translation: 公开了一种用于递增或减少n位数据的计算单元。 该单元具有用于处理n位数据的n / 3个逻辑块，每个逻辑块包括：第一和第二多路复用器，用于传播进位链; 以及耦合到多路复用器的进位链的第一，第二和第三异或（XOR）电路，以产生3位递增的输出。

公开(公告)号：US20080062775A1

公开(公告)日：2008-03-13

申请号：US11852790

申请日：2007-09-10

Applicant: Sung Jo OH

Inventor： Sung Jo OH

IPC: G11C7/10

CPC classification number: H03M7/30 ,  G06F13/1694 ,  G11C7/1006 ,  G11C2207/102

Abstract: A fusion memory device and method that is capable of storing binary data in a compressed format and reading out the compressed binary data in a decompressed format is provided. The fusion memory device includes a main memory for storing data in a compressed format; a secondary memory for buffering binary data to be written within and read from the main memory; and a memory controller having a pair of compressor and decompressor. The memory controller controlling the secondary memory to buffer the binary data downloaded from a host device and the compressor compressing the binary data buffered with the secondary memory in a writing mode. The memory controller controlling the secondary memory to buffer the binary data read out from the main memory within the secondary memory and the decompressor decompressing the binary data buffered within the secondary memory in a reading mode.

Abstract translation: 提供了能够以压缩格式存储二进制数据并以解压缩格式读出压缩的二进制数据的融合存储器件和方法。 融合存储装置包括用于以压缩格式存储数据的主存储器; 辅助存储器，用于缓冲要写入到主存储器中并从主存储器读取的二进制数据; 以及具有一对压缩机和解压缩器的存储器控​​制器。 所述存储器控制器控制所述辅助存储器以缓冲从主机设备下载的二进制数据，并且所述压缩器以写入模式压缩用所述辅助存储器缓冲的二进制数据。 所述存储器控制器控制所述辅助存储器以缓冲从所述辅助存储器中的所述主存储器读出的二进制数据，并且所述解压缩器以读取模式对在所述辅助存储器中缓冲的二进制数据进行解压缩。

公开(公告)号：US20040250010A1

公开(公告)日：2004-12-09

申请号：US10685499

申请日：2003-10-16

Applicant: Carry Computer Eng. Co., Ltd.

Inventor： Chia-Li Chen ,  Hsiang-An Hsieh

IPC: G06F012/00

CPC classification number: G11C7/1006 ,  G11C2207/102

Abstract: The present invention provides a storage device available for increasing storage capacity, mainly comprising a controller and at least a solid-state storage medium; wherein said controller has at least a interface that may be connected to an external system, a microprocessor processing system instructions, and a memory interface communicates to said solid-state storage medium (media); said controller, through an appropriate compressing/decompressing mechanism, compresses original data transferred from the external system to minimized data in 1/N ratio and write it to said solid-state storage medium (media), in order to achieve more storage capacity in said solid-state storage medium (media).

Abstract translation: 本发明提供一种可用于增加存储容量的存储装置，主要包括控制器和至少固态存储介质; 其中所述控制器至少具有可连接到外部系统的接口，微处理器处理系统指令和存储器接口与所述固态存储介质（介质）通信; 所述控制器通过适当的压缩/解压缩机制将从外部系统传送的原始数据压缩为1 / N比的最小化数据并将其写入所述固态存储介质（介质），以便在所述固态存储介质 固态存储介质（介质）。

公开(公告)号：US10055161B1

公开(公告)日：2018-08-21

申请号：US15001784

申请日：2016-01-20

Applicant: EMC Corporation

Inventor： David Meiri ,  Anton Kucherov ,  Vladimir Shveidel

IPC: G06F3/06 ,  G06F11/20

CPC classification number: G06F3/0638 ,  G06F3/0608 ,  G06F3/0619 ,  G06F3/0661 ,  G06F3/0688 ,  G06F11/1068 ,  G06F11/1076 ,  G06F11/108 ,  G06F11/1092 ,  G06F11/2069 ,  G06F2201/85 ,  G06F2211/1014 ,  G11C29/52 ,  G11C2207/102

Abstract: In one aspect, a method includes splitting empty RAID stripes into sub-stripes and storing pages into the sub-stripes based on a compressibility score. In another aspect, a method includes reading pages from 1-stripes, storing compressed data in a temporary location, reading multiple stripes, determining compressibility score for each stripe and filling stripes based on the compressibility score. In a further aspect, a method includes scanning a dirty queue in a system cache, compressing pages ready for destaging, combining compressed pages in to one aggregated page, writing one aggregated page to one stripe and storing pages with same compressibility score in a stripe.

公开(公告)号：US09940230B2

公开(公告)日：2018-04-10

申请号：US13880728

申请日：2011-10-20

Applicant: Monish Shah

Inventor： Monish Shah

IPC: G11C7/10 ,  G06F12/02 ,  G06F3/06 ,  H03M7/30 ,  G11C16/10

CPC classification number: G06F3/0608 ,  G06F3/0641 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/401 ,  G06F2212/7202 ,  G06F2213/0038 ,  G11C7/1006 ,  G11C16/10 ,  G11C2207/102 ,  H03M7/30 ,  H03M7/3084

Abstract: Compression and decompression of data at high speed in solid state storage is described, including accessing a compressed data comprising a plurality of blocks of the compressed data, decompressing each of the plurality of blocks in a first stage of decompression to produce a plurality of partially decompressed blocks, and reconstructing an original data from the partially decompressed blocks in a second stage of decompression.

公开(公告)号：US20170351602A1

公开(公告)日：2017-12-07

申请号：US15545094

申请日：2015-02-27

Applicant: HITACHI, LTD.

Inventor： Masatsugu OSHIMI ,  Yoshihiro OIKAWA ,  Hiroshi HIRAYAMA ,  Junji OGAWA

IPC: G06F12/02 ,  G11C16/04 ,  G06F12/04 ,  G06F3/06 ,  G11C7/10 ,  G11C16/34 ,  G11C11/56

CPC classification number: G06F12/0238 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0649 ,  G06F3/0655 ,  G06F3/0688 ,  G06F12/00 ,  G06F12/04 ,  G11C7/1045 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0475 ,  G11C16/3418 ,  G11C2207/102

Abstract: To determine whether or not to data is compressed at a timing when a non-volatile memory device receives the data from a host apparatus. A storage controller transmits a specified logical address range, an update frequency level of the specified logical address range, and specified data to a device controller. On the basis of the update frequency level of the specified logical address range, the device controller determines whether the specified data is compressed or not. When determination is made that the specified data is compressed, the device controller compresses the specified data to generate compressed data, and writes the compressed data into a non-volatile memory. When determination is made that the specified data is not compressed, the device controller writes the specified data into the non-volatile memory.

公开(公告)号：US20160117244A1

公开(公告)日：2016-04-28

申请号：US14557422

申请日：2014-12-01

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F12/02 ,  G11C16/28

CPC classification number: G06F12/0246 ,  G06F2212/7205 ,  G11C7/1006 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  G11C16/3495 ,  G11C2207/102

Abstract: A data writing method for a rewritable non-volatile memory module is provided. The method includes: compressing data to generate first data; determining whether a data length of the first data meets a predetermined condition. The method also includes: if the data length of the first data meets the predetermined condition, writing the first data into a first physical erasing unit among a plurality of physical erasing units; if the data length of the first data does not meet the predetermined condition, generating dummy data according to a predetermined rule, padding the first data with the dummy data to generate second data and writing the second data into the first physical erasing unit. A data length of the second data meets the predetermined condition.

Abstract translation: 提供了一种用于可重写非易失性存储器模块的数据写入方法。 该方法包括：压缩数据以产生第一数据; 确定第一数据的数据长度是否满足预定条件。 该方法还包括：如果第一数据的数据长度满足预定条件，则将第一数据写入多个物理擦除单元中的第一物理擦除单元; 如果第一数据的数据长度不满足预定条件，则根据预定规则产生伪数据，用伪数据填充第一数据以产生第二数据并将第二数据写入第一物理擦除单元。 第二数据的数据长度满足预定条件。