公开(公告)号：US12041785B1

公开(公告)日：2024-07-16

申请号：US17654383

申请日：2022-03-10

申请人： Kepler Computing Inc.

发明人： Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Debo Olaosebikan ,  Tanay Gosavi ,  Noriyuki Sato ,  Sasikanth Manipatruni

IPC分类号： H10B53/30

CPC分类号： H10B53/30

摘要： A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

公开(公告)号：US12022662B1

公开(公告)日：2024-06-25

申请号：US17552321

申请日：2021-12-15

申请人： Kepler Computing Inc.

发明人： Somilkumar J. Rathi ,  Noriyuki Sato ,  Niloy Mukherjee ,  Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Tanay Gosavi ,  Pratyush Pandey ,  Jason Y. Wu ,  Sasikanth Manipatruni

IPC分类号： H10B53/30

CPC分类号： H10B53/30

摘要： A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.

公开(公告)号：US12016185B1

公开(公告)日：2024-06-18

申请号：US17552293

申请日：2021-12-15

申请人： Kepler Computing Inc.

发明人： Somilkumar J. Rathi ,  Noriyuki Sato ,  Niloy Mukherjee ,  Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Tanay Gosavi ,  Pratyush Pandey ,  Jason Y. Wu ,  Sasikanth Manipatruni

IPC分类号： H10B53/30

CPC分类号： H10B53/30

摘要： A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.

公开(公告)号：US12001266B1

公开(公告)日：2024-06-04

申请号：US17408323

申请日：2021-08-20

申请人： Kepler Computing Inc.

发明人： Amrita Mathuriya ,  Christopher B. Wilkerson ,  Rajeev Kumar Dokania ,  Debo Olaosebikan ,  Sasikanth Manipatruni

IPC分类号： G06F1/32 ,  G06F1/329 ,  G11C5/04 ,  G11C11/00 ,  H01L25/16 ,  G06N20/00

CPC分类号： G06F1/329 ,  G11C5/04 ,  G11C11/005 ,  H01L25/162 ,  G06N20/00 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2924/1441

摘要： A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

公开(公告)号：US11997853B1

公开(公告)日：2024-05-28

申请号：US17654379

申请日：2022-03-10

申请人： Kepler Computing Inc.

发明人： Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Debo Olaosebikan ,  Tanay Gosavi ,  Noriyuki Sato ,  Sasikanth Manipatruni

IPC分类号： H10B53/30

CPC分类号： H10B53/30

摘要： A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

公开(公告)号：US11985832B1

公开(公告)日：2024-05-14

申请号：US17552323

申请日：2021-12-15

申请人： Kepler Computing Inc.

发明人： Somilkumar J. Rathi ,  Noriyuki Sato ,  Niloy Mukherjee ,  Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Tanay Gosavi ,  Pratyush Pandey ,  Jason Y. Wu ,  Sasikanth Manipatruni

IPC分类号： H10B53/30

CPC分类号： H10B53/30

摘要： A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.

公开(公告)号：US11978762B1

公开(公告)日：2024-05-07

申请号：US17654802

申请日：2022-03-14

申请人： Kepler Computing Inc.

发明人： Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Debo Olaosebikan ,  Tanay Gosavi ,  Noriyuki Sato ,  Sasikanth Manipatruni

IPC分类号： G11C11/22 ,  G11C11/419 ,  H01L25/065 ,  H01L49/02 ,  H10B12/00 ,  H10B53/00

CPC分类号： H01L28/55 ,  G11C11/221 ,  G11C11/419 ,  H01L25/0652 ,  H01L28/75 ,  H10B12/20 ,  H10B12/48 ,  H10B53/00

摘要： A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

公开(公告)号：US11942133B2

公开(公告)日：2024-03-26

申请号：US17465796

申请日：2021-09-02

申请人： Kepler Computing, Inc.

发明人： Noriyuki Sato ,  Tanay Gosavi ,  Niloy Mukherjee ,  Amrita Mathuriya ,  Rajeev Kumar Dokania ,  Sasikanth Manipatruni

IPC分类号： H01L21/768 ,  G11C11/22 ,  H01L23/522 ,  H01L23/532 ,  H01L23/535 ,  H01L23/538 ,  H01L49/02 ,  H03K19/185 ,  H10B53/20 ,  H10B53/30

CPC分类号： G11C11/221 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/535 ,  H01L23/5381 ,  H01L23/5386 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H03K19/185 ,  H10B53/20 ,  H10B53/30

摘要： A pocket integration for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

公开(公告)号：US20240088299A1

公开(公告)日：2024-03-14

申请号：US18514998

申请日：2023-11-20

申请人： Kepler Computing Inc.

发明人： Ramesh Ramamoorthy ,  Sasikanth Manipatruni ,  Gaurav Thareja

IPC分类号： H01L29/786 ,  H01L29/20 ,  H01L29/66 ,  H01L29/737 ,  H01L29/74 ,  H10B53/30

CPC分类号： H01L29/78618 ,  H01L28/56 ,  H01L28/57 ,  H01L28/60 ,  H01L28/65 ,  H01L29/2003 ,  H01L29/6684 ,  H01L29/7375 ,  H01L29/7408 ,  H01L29/7869 ,  H10B53/30 ,  H10B12/36

摘要： The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor, which in turn comprises a polar layer comprising a crystalline base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen, wherein the dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor additionally comprises first and second crystalline conductive or semiconductive oxide electrodes on opposing sides of the polar layer, wherein the polar layer has a lattice constant that is matched within about 20% of a lattice constant of one or both of the first and second crystalline conductive or semiconductive oxide electrodes. The first crystalline conductive or semiconductive oxide electrode serves as a template for growing the polar layer thereon, such that at least a portion of the polar layer is pseudomorphically formed on the first crystalline conductive or semiconductive oxide electrode.

公开(公告)号：US11910618B1

公开(公告)日：2024-02-20

申请号：US17654562

申请日：2022-03-11

申请人： Kepler Computing Inc.

发明人： Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Debo Olaosebikan ,  Tanay Gosavi ,  Noriyuki Sato ,  Sasikanth Manipatruni

IPC分类号： H10B53/30 ,  G11C11/22 ,  H10B53/10

CPC分类号： H10B53/30 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293 ,  H10B53/10

摘要： A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.