公开(公告)号：US12107143B2

公开(公告)日：2024-10-01

申请号：US17813504

申请日：2022-07-19

申请人： NXP B.V.

发明人： Ljubo Radic ,  Johannes Josephus Theodorus Marinus Donkers ,  Bernhard Grote

IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L29/737

CPC分类号： H01L29/66242 ,  H01L29/1004 ,  H01L29/7375 ,  H01L29/7378

摘要： A semiconductor device, such as a heterojunction bipolar transistor (HBT), may include an extrinsic base region that is connected to a collector region via semiconductor material formed in an opening in one or more dielectric layers interposed between the extrinsic base region and the collector region. The extrinsic base region may be formed from monocrystalline semiconductor material, such as silicon or silicon germanium, via selective epitaxial growth. An intrinsic base region may be formed adjacent to the extrinsic base region and may be interposed directly between the collector region and an intrinsic emitter region. A HBT with such an arrangement may have reduced base-collector capacitance and reduced base resistance compared to some conventional HBTs.

公开(公告)号：US20240204052A1

公开(公告)日：2024-06-20

申请号：US18066110

申请日：2022-12-14

申请人： NXP B.V.

发明人： Jay Paul John ,  James Albert Kirchgessner

IPC分类号： H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/737

CPC分类号： H01L29/1004 ,  H01L29/0817 ,  H01L29/66242 ,  H01L29/7375 ,  H01L29/0649

摘要： A semiconductor device, such as a heterojunction bipolar transistor (HBT), may include an extrinsic base region an intrinsic base region, and a lateral base link region disposed between and in contact with each of the extrinsic base region and an intrinsic base region. The extrinsic base region, the lateral base link region, and a portion of the intrinsic base region each may be formed on a passivation layer disposed over an isolation region and a collector region of a substrate of the semiconductor device. The extrinsic base region and a first portion of the lateral base link region may be formed from polycrystalline semiconductor material. The intrinsic base region and a second portion of the lateral base link region may be formed from monocrystalline semiconductor material. The lateral base link region may be formed after formation of the extrinsic base region and the intrinsic base region.

公开(公告)号：US11916149B2

公开(公告)日：2024-02-27

申请号：US17814330

申请日：2022-07-22

申请人： Kepler Computing Inc.

发明人： Ramesh Ramamoorthy ,  Sasikanth Manipatruni ,  Gaurav Thareja

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L29/20 ,  H01L29/74 ,  H01L29/737 ,  H10B53/30 ,  H10B12/00 ,  H01L49/02

CPC分类号： H01L29/78618 ,  H01L28/56 ,  H01L28/57 ,  H01L28/60 ,  H01L28/65 ,  H01L29/2003 ,  H01L29/6684 ,  H01L29/7375 ,  H01L29/7408 ,  H01L29/7869 ,  H10B53/30 ,  H10B12/312 ,  H10B12/36

摘要： The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a transistor formed on a silicon substrate and a capacitor electrically connected to the transistor by a conductive via. The capacitor comprises upper and lower conductive oxide electrodes on opposing sides of a polar layer, wherein the lower conductive oxide electrode is electrically connected to a drain of the transistor. The capacitor additionally comprises a polar layer comprising a base polar material doped with a dopant, wherein the base polar material includes one or more metal elements and one or both of oxygen or nitrogen, wherein the dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The semiconductor device additionally comprises a lower barrier layer comprising a refractory metal or an intermetallic compound between the lower conductive oxide electrode and the conductive via.

公开(公告)号：US11757043B2

公开(公告)日：2023-09-12

申请号：US17819601

申请日：2022-08-12

申请人： Kepler Computing Inc.

发明人： Ramesh Ramamoorthy ,  Sasikanth Manipatruni ,  Gaurav Thareja

IPC分类号： H01L29/00 ,  H01L29/786 ,  H01L29/66 ,  H01L29/20 ,  H01L29/74 ,  H01L29/737 ,  H01L49/02 ,  H10B53/30 ,  H10B12/00

CPC分类号： H01L29/78618 ,  H01L28/56 ,  H01L28/57 ,  H01L28/65 ,  H01L29/2003 ,  H01L29/6684 ,  H01L29/7375 ,  H01L29/7408 ,  H01L29/7869 ,  H10B53/30 ,  H10B12/312 ,  H10B12/36

摘要： The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer. The capacitor stack further comprises first and second barrier metal layers on respective ones of the first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.

公开(公告)号：US20230155029A1

公开(公告)日：2023-05-18

申请号：US17815100

申请日：2022-07-26

申请人： Kepler Computing Inc.

发明人： Ramesh Ramamoorthy ,  Sasikanth Manipatruni ,  Gaurav Thareja

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L29/20 ,  H01L29/74 ,  H01L29/737 ,  H10B53/30

CPC分类号： H01L29/78618 ,  H01L29/6684 ,  H01L29/2003 ,  H01L29/7408 ,  H01L29/7869 ,  H01L29/7375 ,  H01L28/65 ,  H01L28/56 ,  H01L28/57 ,  H10B53/30 ,  H10B12/36

摘要： The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a capacitor comprises a crystalline polar layer comprising a base polar material substitutionally doped with a dopant. The base polar material comprises one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element of one of 4d series, 5d series, 4f series or 5f series that is different from the one or more metal elements, such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV.

公开(公告)号：US20180226254A1

公开(公告)日：2018-08-09

申请号：US15794418

申请日：2017-10-26

申请人： Ideal Power Inc.

发明人： Richard A. Blanchard ,  William C. Alexander

IPC分类号： H01L21/265 ,  H03K17/66 ,  H01L29/08 ,  H01L21/225 ,  H01L21/283 ,  H01L29/739 ,  H01L29/737 ,  H01L29/732 ,  H01L29/66 ,  H01L29/16 ,  H01L21/18 ,  H01L29/06 ,  H01L21/78 ,  H01L21/683 ,  H01L21/324 ,  H01L21/306 ,  H01L21/304 ,  H01L29/423

CPC分类号： H01L21/265 ,  H01L21/187 ,  H01L21/2252 ,  H01L21/283 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/324 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L29/0619 ,  H01L29/0821 ,  H01L29/1604 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/7397 ,  H01L2221/68304 ,  H01L2221/68327 ,  H03K17/66

摘要： Methods and systems for double-sided semiconductor device fabrication. Devices having multiple leads on each surface can be fabricated using a high-temperature-resistant handle wafer and a medium-temperature-resistant handle wafer. Dopants can be introduced on both sides shortly before a single long high-temperature diffusion step diffuses all dopants to approximately equal depths on both sides. All high-temperature processing occurs with no handle wafer or with a high-temperature handle wafer attached. Once a medium-temperature handle wafer is attached, no high-temperature processing steps occur. High temperatures can be considered to be those which can result in damage to the device in the presence of aluminum-based metallizations.

公开(公告)号：US09647553B2

公开(公告)日：2017-05-09

申请号：US15164436

申请日：2016-05-25

申请人： Ideal Power Inc.

发明人： William C. Alexander ,  Richard A. Blanchard

IPC分类号： H02M3/158 ,  H01L29/732 ,  H01L29/739 ,  H03K17/66

CPC分类号： H02M3/158 ,  H01L27/0755 ,  H01L27/0823 ,  H01L27/0828 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/16 ,  H01L29/1604 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/7393 ,  H01L29/7395 ,  H02M1/088 ,  H02M3/1582 ,  H02M7/797 ,  H02M11/00 ,  H03K3/012 ,  H03K17/60 ,  H03K17/66 ,  H03K17/687

摘要： Methods, systems, circuits, and devices for power-packet-switching power converters using bidirectional bipolar transistors (BTRANs) for switching. Four-terminal three-layer BTRANs provide substantially identical operation in either direction with forward voltages of less than a diode drop. BTRANs are fully symmetric merged double-base bidirectional bipolar opposite-faced devices which operate under conditions of high non-equilibrium carrier concentration, and which can have surprising synergies when used as bidirectional switches for power-packet-switching power converters. BTRANs are driven into a state of high carrier concentration, making the on-state voltage drop very low.

公开(公告)号：US20170085179A1

公开(公告)日：2017-03-23

申请号：US15164436

申请日：2016-05-25

申请人： Ideal Power Inc.

发明人： William C. Alexander ,  Richard A. Blanchard

IPC分类号： H02M3/158 ,  H01L29/739 ,  H03K17/66 ,  H01L29/732

CPC分类号： H02M3/158 ,  H01L27/0755 ,  H01L27/0823 ,  H01L27/0828 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/16 ,  H01L29/1604 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/7393 ,  H01L29/7395 ,  H02M1/088 ,  H02M3/1582 ,  H02M7/797 ,  H02M11/00 ,  H03K3/012 ,  H03K17/60 ,  H03K17/66 ,  H03K17/687

摘要： Methods, systems, circuits, and devices for power-packet-switching power converters using bidirectional bipolar transistors (BTRANs) for switching. Four-terminal three-layer BTRANs provide substantially identical operation in either direction with forward voltages of less than a diode drop. BTRANs are fully symmetric merged double-base bidirectional bipolar opposite-faced devices which operate under conditions of high non-equilibrium carrier concentration, and which can have surprising synergies when used as bidirectional switches for power-packet-switching power converters. BTRANs are driven into a state of high carrier concentration, making the on-state voltage drop very low.

公开(公告)号：US20160285388A1

公开(公告)日：2016-09-29

申请号：US15004872

申请日：2016-01-22

申请人： Ideal Power Inc.

发明人： William C. Alexander

IPC分类号： H02M7/537 ,  H01L29/10 ,  H01L29/747

CPC分类号： H01L29/1004 ,  H01L29/0619 ,  H01L29/0804 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/16 ,  H01L29/1604 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/747 ,  H02M3/1582 ,  H02M7/487 ,  H03K17/60 ,  H03K17/66

摘要： Power is inverted using double-base-contact bidirectional bipolar transistors in a three-level-inverter topology. The transistors not only switch to synthesize a PWM approximation of the desired AC waveform, but also have transient phases of diode conduction before each full turn-on or turn-off.

摘要翻译： 在三电平逆变器拓扑中使用双基极接触式双向双极晶体管对电源进行反相。 晶体管不仅可以切换为合成所需AC波形的PWM近似，而且在每次完全导通或关断之前也具有二极管导通的瞬态相位。

公开(公告)号：US09355853B2

公开(公告)日：2016-05-31

申请号：US14566576

申请日：2014-12-10

申请人： Ideal Power Inc.

发明人： Richard A. Blanchard ,  William C. Alexander

IPC分类号： H01L21/67 ,  H01L21/304 ,  H01L21/683 ,  H01L29/737 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H03K17/66 ,  H01L29/732 ,  H01L29/66 ,  H01L29/739 ,  H01L21/225 ,  H01L29/423

CPC分类号： H01L21/265 ,  H01L21/187 ,  H01L21/2252 ,  H01L21/283 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/324 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L29/0619 ,  H01L29/0821 ,  H01L29/1604 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/7397 ,  H01L2221/68304 ,  H01L2221/68327 ,  H03K17/66

摘要： Methods and systems for double-sided semiconductor device fabrication. Devices having multiple leads on each surface can be fabricated using a high-temperature-resistant handle wafer and a medium-temperature-resistant handle wafer. Dopants can be introduced on both sides shortly before a single long high-temperature diffusion step diffuses all dopants to approximately equal depths on both sides. All high-temperature processing occurs with no handle wafer or with a high-temperature handle wafer attached. Once a medium-temperature handle wafer is attached, no high-temperature processing steps occur. High temperatures can be considered to be those which can result in damage to the device in the presence of aluminum-based metallizations.

摘要翻译： 双面半导体器件制造的方法和系统。 在每个表面上具有多个引线的器件可以使用耐高温处理晶片和中温耐用的晶片来制造。 在单个长的高温扩散步骤之前不久可以在两侧引入掺杂剂，将所有掺杂剂扩散到两侧的大致相等的深度。 所有的高温处理都是在没有处理晶片的情况下进行的，或者附着有高温处理晶片。 一旦安装了中温处理晶片，则不会发生高温处理步骤。 可以认为高温可能是在存在铝基金属化时可能导致器件损坏的那些。