公开(公告)号：US20230197797A1

公开(公告)日：2023-06-22

申请号：US17645280

申请日：2021-12-20

Applicant: NXP B.V.

Inventor： Congyong Zhu ,  Bernhard Grote ,  Bruce McRae Green

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/778 ,  H01L21/311 ,  H01L21/76 ,  H01L21/765 ,  H01L29/66

CPC classification number: H01L29/402 ,  H01L21/765 ,  H01L21/7605 ,  H01L21/31116 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/66462

Abstract: Placement of a field plate in a field-effect transistor is optimized by using multiple dielectric layers such that a first end of field plate is separated from a channel region of the transistor by a first set of one or more distinct dielectric material layers. A second end of the field plate overlies the channel region and a control electrode from which it is separated by the first set of dielectric layers and one or more additional dielectric layers.

公开(公告)号：US20220208975A1

公开(公告)日：2022-06-30

申请号：US17139636

申请日：2020-12-31

Applicant: NXP B.V.

Inventor： Ibrahim Khalil ,  Bernhard Grote ,  Humayun Kabir ,  Bruce McRae Green

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first dielectric layer disposed over the upper surface of the semiconductor substrate, and a first current-carrying electrode and a second current-carrying electrode formed over the semiconductor substrate within openings formed in the first dielectric layer. A control electrode is formed over the semiconductor substrate and disposed between the first current-carrying electrode and a second current-carrying electrode and over the first dielectric layer. A first conductive element is formed over the first dielectric layer, adjacent the control electrode and between the control electrode and the second current-carrying electrode. A second dielectric layer is disposed over the control electrode and over the first conductive element. A second conductive element is disposed over the second dielectric layer and over the first conductive element.

公开(公告)号：US10418483B2

公开(公告)日：2019-09-17

申请号：US15797450

申请日：2017-10-30

Applicant: NXP B.V.

Inventor： Bernhard Grote ,  Xin Lin ,  Saumitra Raj Mehrotra ,  Ljubo Radic ,  Ronghua Zhu

IPC: H01L21/761 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L29/36 ,  H01L29/08 ,  H01L29/49 ,  H01L29/40

Abstract: An example laterally diffused metal oxide semiconducting (LDMOS) device includes a semiconductor substrate of a first conductivity type, active MOS regions, and a lightly-doped isolation layer (LDIL) of a second conductivity type. The active MOS regions include source and drain regions and a plurality of PN junctions. The LDIL is formed above and laterally along the semiconductor substrate, and located between the semiconductor substrate and at least a part of the active MOS regions. The LDIL is doped with dopant of the second conductivity type to cause, in response to selected voltages applied to the LDMOS device, the plurality of PN junctions to deplete each other and to support a voltage drop between the source and drain regions along the LDIL.

公开(公告)号：US12148820B2

公开(公告)日：2024-11-19

申请号：US17645286

申请日：2021-12-20

Applicant: NXP B.V.

Inventor： Congyong Zhu ,  Bernhard Grote ,  Bruce McRae Green

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66

Abstract: Placement of a field plate in a field-effect transistor is optimized by using multiple dielectric layers such that a first end of field plate is separated from a channel region of the transistor by a first set of one or more distinct dielectric material layers. A second end of the field plate overlies the channel region and a control electrode from which it is separated by the first set of dielectric layers and one or more additional dielectric layers.

公开(公告)号：US11923424B2

公开(公告)日：2024-03-05

申请号：US17139636

申请日：2020-12-31

Applicant: NXP B.V.

Inventor： Ibrahim Khalil ,  Bernhard Grote ,  Humayun Kabir ,  Bruce McRae Green

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/402 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/404 ,  H01L29/66462 ,  H01L29/78

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first dielectric layer disposed over the upper surface of the semiconductor substrate, and a first current-carrying electrode and a second current-carrying electrode formed over the semiconductor substrate within openings formed in the first dielectric layer. A control electrode is formed over the semiconductor substrate and disposed between the first current-carrying electrode and a second current-carrying electrode and over the first dielectric layer. A first conductive element is formed over the first dielectric layer, adjacent the control electrode and between the control electrode and the second current-carrying electrode. A second dielectric layer is disposed over the control electrode and over the first conductive element. A second conductive element is disposed over the second dielectric layer and over the first conductive element.

公开(公告)号：US20240030308A1

公开(公告)日：2024-01-25

申请号：US17813504

申请日：2022-07-19

Applicant: NXP B.V.

Inventor： Ljubo Radic ,  Johannes Josephus Theodorus Marinus Donkers ,  Bernhard Grote

IPC: H01L29/66 ,  H01L29/737 ,  H01L29/10

CPC classification number: H01L29/66242 ,  H01L29/7378 ,  H01L29/7375 ,  H01L29/1004

Abstract: A semiconductor device, such as a heterojunction bipolar transistor (HBT), may include an extrinsic base region that is connected to a collector region via semiconductor material formed in an opening in one or more dielectric layers interposed between the extrinsic base region and the collector region. The extrinsic base region may be formed from monocrystalline semiconductor material, such as silicon or silicon germanium, via selective epitaxial growth. An intrinsic base region may be formed adjacent to the extrinsic base region and may be interposed directly between the collector region and an intrinsic emitter region. A HBT with such an arrangement may have reduced base-collector capacitance and reduced base resistance compared to some conventional HBTs.

公开(公告)号：US12107143B2

公开(公告)日：2024-10-01

申请号：US17813504

申请日：2022-07-19

Applicant: NXP B.V.

Inventor： Ljubo Radic ,  Johannes Josephus Theodorus Marinus Donkers ,  Bernhard Grote

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/737

CPC classification number: H01L29/66242 ,  H01L29/1004 ,  H01L29/7375 ,  H01L29/7378

Abstract: A semiconductor device, such as a heterojunction bipolar transistor (HBT), may include an extrinsic base region that is connected to a collector region via semiconductor material formed in an opening in one or more dielectric layers interposed between the extrinsic base region and the collector region. The extrinsic base region may be formed from monocrystalline semiconductor material, such as silicon or silicon germanium, via selective epitaxial growth. An intrinsic base region may be formed adjacent to the extrinsic base region and may be interposed directly between the collector region and an intrinsic emitter region. A HBT with such an arrangement may have reduced base-collector capacitance and reduced base resistance compared to some conventional HBTs.

公开(公告)号：US20240250130A1

公开(公告)日：2024-07-25

申请号：US18593544

申请日：2024-03-01

Applicant: NXP B.V.

Inventor： Ibrahim Khalil ,  Bernhard Grote ,  Humayun Kabir ,  Bruce McRae Green

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/402 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/404 ,  H01L29/66462 ,  H01L29/78

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first dielectric layer disposed over the upper surface of the semiconductor substrate, and a first current-carrying electrode and a second current-carrying electrode formed over the semiconductor substrate within openings formed in the first dielectric layer. A control electrode is formed over the semiconductor substrate and disposed between the first current-carrying electrode and a second current-carrying electrode and over the first dielectric layer. A first conductive element is formed over the first dielectric layer, adjacent the control electrode and between the control electrode and the second current-carrying electrode. A second dielectric layer is disposed over the control electrode and over the first conductive element. A second conductive element is disposed over the second dielectric layer and over the first conductive element. An opening in the second dielectric layer couples the first conductive element to the second conductive element.

公开(公告)号：US20240055314A1

公开(公告)日：2024-02-15

申请号：US17818607

申请日：2022-08-09

Applicant: NXP B.V.

Inventor： Ljubo Radic ,  Richard Emil Sweeney ,  Vikas Shilimkar ,  Bernhard Grote ,  Darrell Glenn Hill ,  Ibrahim Khalil

IPC: H01L23/367 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L23/367 ,  H01L29/2003 ,  H01L29/7786

Abstract: A transistor formed in a semiconductor substrate is provided with a cooling trench. The cooling trench is elongated and extends laterally from a first end of an elongated gate electrode disposed above a channel region of the transistor to a second end of the gate electrode in a first direction that is parallel to a top surface of the semiconductor substrate. The cooling trench is coupled to the first current terminal and extends laterally from a first end to a second end of the first elongated cooling trench along the first direction and extends vertically from the first current terminal and through the top surface into the semiconductor substrate. The cooling trench is filled throughout with a thermally-conductive material configured to dissipate heat from the channel region into the semiconductor substrate.

公开(公告)号：US20230197839A1

公开(公告)日：2023-06-22

申请号：US17645286

申请日：2021-12-20

Applicant: NXP B.V.

Inventor： Congyong Zhu ,  Bernhard Grote ,  Bruce McRae Green

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/778 ,  H01L29/66462 ,  H01L29/2003

Abstract: Placement of a field plate in a field-effect transistor is optimized by using multiple dielectric layers such that a first end of field plate is separated from a channel region of the transistor by a first set of one or more distinct dielectric material layers. A second end of the field plate overlies the channel region and a control electrode from which it is separated by the first set of dielectric layers and one or more additional dielectric layers.