公开(公告)号：US11973495B2

公开(公告)日：2024-04-30

申请号：US18161802

申请日：2023-01-30

申请人： pSemi Corporation

发明人： Simon Edward Willard

IPC分类号： H04B1/48 ,  H03H11/02 ,  H03K17/687 ,  H04B1/44

CPC分类号： H03K17/6874 ,  H03H11/02 ,  H04B1/44 ,  H04B1/48

摘要： Methods and devices to address body leakage current generation and bias voltage distribution associated with body leakage current in an OFF state of a FET switch stack are disclosed. The devices include charge redistribution arrangements and bridge networks to perform coupling/decoupling to/from the FET switch stack. Detailed structures of such bridge networks are also described.

公开(公告)号：US20230065101A1

公开(公告)日：2023-03-02

申请号：US17858739

申请日：2022-07-06

申请人： pSemi Corporation

发明人： Befruz Tasbas ,  Simon Edward Willard ,  Alain Duvallet ,  Sinan Goktepeli

IPC分类号： H01L27/092 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/45

摘要： Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.

公开(公告)号：US11569812B2

公开(公告)日：2023-01-31

申请号：US16902032

申请日：2020-06-15

申请人： pSemi Corporation

发明人： Eric S. Shapiro ,  Simon Edward Willard

IPC分类号： H03K17/687 ,  H03K17/693

摘要： Methods and devices to address the undesired DC voltage distribution across switch stacks in OFF state are disclosed. The disclosed devices include charge control elements that sample the RF signal to generate superimposed voltages at specific points of the switch stack biasing circuit. The provided voltages help reducing the drooping voltages on drain/source/body terminals of the transistors within the stack by supplying the current drawn by drain/source terminals of the stacked transistors and/or by sinking the body leakage current exiting the body terminals of such transistors. Methods and techniques teaching how to provide proper tapping points in the biasing circuit to sample the RF signal are also disclosed.

公开(公告)号：US11469296B2

公开(公告)日：2022-10-11

申请号：US16929988

申请日：2020-07-15

申请人： pSemi Corporation

发明人： Abhijeet Paul ,  Simon Edward Willard ,  Alain Duvallet

IPC分类号： H01L29/06 ,  H01L21/762 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/36 ,  H01L29/423 ,  H01L29/10

摘要： FET designs that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments includes nFET designs in which the work function ΦMF of the gate structure overlying the edge transistors of the nFET is increased by forming extra P+ implant regions within at least a portion of the gate structure, thereby increasing the Vt of the edge transistors to a level that may exceed the Vt of the central conduction channel of the nFET. In some embodiments, the gate structure of the nFET is modified to increase or “flare” the effective channel length of the edge transistors relative to the length of the central conduction channel of the FET. Other methods of changing the work function ΦMF of the gate structure overlying the edge transistors are also disclosed. The methods may be adapted to fabricating pFETs by reversing or substituting material types.

公开(公告)号：US11251140B2

公开(公告)日：2022-02-15

申请号：US16875615

申请日：2020-05-15

申请人： pSemi Corporation

发明人： Robert Mark Englekirk ,  Keith Bargroff ,  Christopher C. Murphy ,  Tero Tapio Ranta ,  Simon Edward Willard

IPC分类号： H03B1/00 ,  H03K3/00 ,  H01L23/60 ,  H01L27/12 ,  H01L29/786 ,  H03K17/687 ,  H01L23/552 ,  H01L29/10 ,  H01L23/66 ,  H03K17/0412 ,  H01L21/762 ,  H03K17/0416 ,  H03K17/042 ,  H03K17/14

摘要： Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same VDS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same VGS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both VGS and VDS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.

公开(公告)号：US11049855B2

公开(公告)日：2021-06-29

申请号：US16059978

申请日：2018-08-09

申请人： pSemi Corporation

发明人： Eric S. Shapiro ,  Simon Edward Willard ,  Tero Tapio Ranta

IPC分类号： H01L27/06 ,  H01L29/93 ,  H01L23/66

摘要： Overcoming parasitic capacitances in RF integrated circuits is a challenging problem. The disclosed methods and devices provide solution to such challenge. Devices based on tunable capacitive elements that can be implemented with switch RF stacks are also disclosed.

公开(公告)号：US10923592B2

公开(公告)日：2021-02-16

申请号：US16431155

申请日：2019-06-04

申请人： pSemi Corporation

发明人： Abhijeet Paul ,  Simon Edward Willard ,  Alain Duvallet

IPC分类号： H01L29/78 ,  H01L27/12 ,  H01L21/84 ,  H01L29/10 ,  H01L29/66 ,  H01L21/74 ,  H01L29/786 ,  H01L29/40 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06

摘要： A high-voltage switching device that can be fabricated in a standard low-voltage process, such as CMOS, and more specifically SOI CMOS. Embodiments include integrated circuits that combine, in a unitary structure, a FET device and an integrated, co-fabricated modulated resistance region (MRR) controlled by one or more Voltage-Drop Modulation Gates (VDMGs). The VDMGs are generally biased independently of the gate of the FET device, and in such a way as to protect each VDMG from excessive and potentially destructive voltages. In a first embodiment, an integrated circuit high voltage switching device includes a transistor structure including a source, a gate, and an internal drain; an MRR connected to the internal drain of the transistor structure; at least one VDMG that controls the resistance of the MRR; and a drain electrically connected to the MRR. Each VDMG at least partially depletes the MRR upon application of a bias voltage.

公开(公告)号：US10770480B2

公开(公告)日：2020-09-08

申请号：US16422648

申请日：2019-05-24

申请人： pSemi Corporation

发明人： Buddhika Abesingha ,  Simon Edward Willard ,  Alain Duvallet ,  Merlin Green ,  Sivakumar Kumarasamy

IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L21/66 ,  H01L23/538 ,  H01L23/535 ,  H01L29/786 ,  H01L21/74

摘要： Systems, methods and apparatus for coexistence of high voltage and low voltage devices and circuits on a same integrated circuit fabricated in silicon-on-insulator (SOI) technology are described. In particular, techniques for mitigating back gate effects are described, including using of resistive and/or capacitive couplings to control surface potentials at regions of a substrate used for the SOI fabrication proximate the high voltage and low voltage devices and circuits. In one case, an N-type implant is used to provide a high potential differential with respect to a substrate potential.

公开(公告)号：US20200091148A1

公开(公告)日：2020-03-19

申请号：US16580088

申请日：2019-09-24

申请人： pSemi Corporation

发明人： Befruz Tasbas ,  Simon Edward Willard ,  Alain Duvallet ,  Sinan Goktepeli

IPC分类号： H01L27/092 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/45

摘要： Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.

公开(公告)号：US10546747B2

公开(公告)日：2020-01-28

申请号：US16167424

申请日：2018-10-22

申请人： pSemi Corporation

发明人： Robert Mark Englekirk ,  Keith Bargroff ,  Christopher C. Murphy ,  Tero Tapio Ranta ,  Simon Edward Willard

IPC分类号： H01L29/06 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/322 ,  H01L21/265 ,  H01L21/762 ,  H01L27/12

摘要： Modified silicon-on-insulator (SOI) substrates having a trap rich layer, and methods for making such modifications. The modified regions eliminate or manage accumulated charge that would otherwise arise because of the interaction of the underlying trap rich layer and active layer devices undergoing transient changes of state, thereby eliminating or mitigating the effects of such accumulated charge on non-RF integrated circuitry fabricated on such substrates. Embodiments retain the beneficial characteristics of SOI substrates with a trap rich layer for RF circuitry requiring high linearity, such as RF switches, while avoiding the problems of a trap rich layer for circuitry that is sensitive to accumulated charge effects caused by the presence of the trap rich layer, such as non-RF analog circuitry and amplifiers (including power amplifiers and low noise amplifiers).