公开(公告)号：US20100148275A1

公开(公告)日：2010-06-17

申请号：US12712890

申请日：2010-02-25

Applicant: Yoshihiro SATO ,  Atsuhiro KAJIYA

Inventor： Yoshihiro SATO ,  Atsuhiro KAJIYA

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/823807 ,  H01L29/513 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7843

Abstract: A semiconductor device includes a first MIS transistor formed on a first active region, and a second MIS transistor formed on a second active region. The first MIS transistor includes a first gate insulating film, and a first gate electrode including a first metal film and a first silicon film. The second MIS transistor includes a second gate insulating film, and a second gate electrode including the first metal film, a second metal film, and a second silicon film.

Abstract translation: 半导体器件包括形成在第一有源区上的第一MIS晶体管和形成在第二有源区上的第二MIS晶体管。 第一MIS晶体管包括第一栅极绝缘膜和包括第一金属膜和第一硅膜的第一栅电极。 第二MIS晶体管包括第二栅极绝缘膜和包括第一金属膜，第二金属膜和第二硅膜的第二栅电极。

公开(公告)号：US20120056270A1

公开(公告)日：2012-03-08

申请号：US13294727

申请日：2011-11-11

Applicant: Tomohiro FUJITA ,  Junji HIRASE ,  Yoshihiro SATO

Inventor： Tomohiro FUJITA ,  Junji HIRASE ,  Yoshihiro SATO

IPC: H01L27/092

CPC classification number: H01L29/4983 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/513 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/7833

Abstract: A semiconductor device includes an NMIS transistor including a first gate insulating film containing a high-k dielectric and a first gate electrode provided on the first gate insulating film and containing a metal material and a PMIS transistor including a second gate insulating film containing a high-k dielectric and a second gate electrode provided on the second gate insulating film and containing a metal material. A side surface of the first gate insulating film is located at an inner side of a side surface of the first gate electrode. A ratio of a length of the first gate insulating film along a gate length direction to a length of the first gate electrode along the gate length direction is lower than a ratio of a length of the second gate insulating film along the gate length direction to a length of the second gate electrode along the gate length direction.

Abstract translation: 半导体器件包括NMIS晶体管，其包括含有高k电介质的第一栅极绝缘膜和设置在第一栅极绝缘膜上并且包含金属材料的第一栅电极和包含含有高k电介质的第二栅极绝缘膜的PMIS晶体管， k电介质和设置在所述第二栅极绝缘膜上并且包含金属材料的第二栅电极。 第一栅极绝缘膜的侧面位于第一栅电极的侧面的内侧。 第一栅极绝缘膜沿着栅极长度方向的长度与栅极长度方向上的第一栅电极的长度的比率小于栅极长度方向上的第二栅极绝缘膜的长度与栅极长度方向的长度的比 沿栅极长度方向的第二栅电极的长度。

公开(公告)号：US20110073931A1

公开(公告)日：2011-03-31

申请号：US12942057

申请日：2010-11-09

Applicant: Yoshihiro HIROTA ,  Yoshihiro SATO ,  Nobuo OKUMURA

Inventor： Yoshihiro HIROTA ,  Yoshihiro SATO ,  Nobuo OKUMURA

IPC: H01L29/788 ,  H01L21/306

CPC classification number: H01L27/11521 ,  H01L21/0214 ,  H01L21/02332 ,  H01L21/28273 ,  H01L21/31111 ,  H01L21/3144 ,  H01L21/3211 ,  H01L21/76232 ,  H01L29/42336 ,  H01L29/7881

Abstract: A plasma nitriding process is followed by a selective etching process which removes a silicon oxynitride film formed on surfaces of both an element separation film and an insulation film while leaving a silicon nitride film formed on an electrode layer. The selective etching process removes the silicon oxynitride film formed on the surfaces of the element separation film and the insulation film.

Abstract translation: 等离子体氮化处理之后是选择性蚀刻工艺，其除去在元件分离膜和绝缘膜的表面上形成的氮氧化硅膜，同时留下形成在电极层上的氮化硅膜。 选择性蚀刻工艺除去在元件分离膜和绝缘膜的表面上形成的氧氮化硅膜。

公开(公告)号：US20110053381A1

公开(公告)日：2011-03-03

申请号：US12866145

申请日：2010-08-04

Applicant: Takashi KOBAYASHI ,  Daisuke KATAYAMA ,  Yoshihiro SATO ,  Junji HORII ,  Yoshihiro HIROTA

Inventor： Takashi KOBAYASHI ,  Daisuke KATAYAMA ,  Yoshihiro SATO ,  Junji HORII ,  Yoshihiro HIROTA

IPC: H01L21/465

CPC classification number: H01L21/3105 ,  H01J37/32192 ,  H01J37/3222 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/67167 ,  H01L21/76232 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/66795

Abstract: Disclosed is a method for modifying an insulating film with plasma using a plasma processing apparatus which introduces a microwave into a processing chamber through a plane antenna having a plurality of holes. Processing gas containing a noble gas and oxygen is introduced into the processing chamber and microwave is introduced into the processing chamber through the plane antenna. Plasma composed mainly of O2+ ions and O(1D2) radicals is generated in a pressure condition within a range of 6.7 Pa to 267 Pa to modify the insulating film with the plasma.

Abstract translation: 公开了一种使用等离子体处理装置等离子体修饰绝缘膜的方法，其通过具有多个孔的平面天线将微波引入处理室。 含有惰性气体和氧气的处理气体被引入处理室，微波通过平面天线被引入处理室。 在6.7Pa至267Pa的压力条件下产生主要由O 2 +离子和O（1D 2）基团组成的等离子体，以等离子体改性绝缘膜。

公开(公告)号：US20080030906A1

公开(公告)日：2008-02-07

申请号：US11848697

申请日：2007-08-31

Applicant: Yoshihiro SATO

Inventor： Yoshihiro SATO

IPC: G11B5/33

CPC classification number: H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  H01L27/228 ,  H01L43/12

Abstract: A magnetoresistive effect element comprises a first magnetic layer having a pinned magnetization direction, and a second magnetic layer having a magnetization direction changed corresponding to an outside magnetic field. A resistance state is changed corresponding to the magnetization direction of the second magnetic layer corresponding to the magnetization direction of the first magnetic layer. The second magnetic layer has a first recess which is dented toward an inside in one side parallel with a hard magnetization axis direction and a second recess dented toward the inside in the other side parallel with the hard magnetization axis direction.

Abstract translation: 磁阻效应元件包括具有钉扎磁化方向的第一磁性层和具有相应于外部磁场变化的磁化方向的第二磁性层。 对应于与第一磁性层的磁化方向对应的第二磁性层的磁化方向，电阻状态改变。 第二磁性层具有与硬磁化轴方向平行的一侧的内侧凹陷的第一凹部和与硬磁化轴方向平行的另一侧的向内侧凹陷的第二凹部。

公开(公告)号：US20130027057A1

公开(公告)日：2013-01-31

申请号：US13279323

申请日：2011-10-23

Applicant: Hisao HORI ,  Yoshikazu ABE ,  Yoshihiro SATO

Inventor： Hisao HORI ,  Yoshikazu ABE ,  Yoshihiro SATO

IPC: G01R31/00 ,  H01H57/00 ,  H01H11/00

CPC classification number: G01R31/06 ,  G01R31/3277 ,  H01H57/00 ,  H01H2057/006 ,  Y10T29/49105

Abstract: A package of a switching apparatus that houses an actuator having a movable contact point and in which a fixed contact point, which is electrically connected to or disconnected form the movable contact point, is accurately formed. Provided is a switching apparatus comprising a first substrate provided with a via that electrically connects a top surface thereof and a bottom surface thereof, while maintaining an air-tight state between the top surface and the bottom surface; a second substrate provided on the first substrate and in which is formed a through-hole that houses an actuator; and a third substrate provided on the second substrate and supporting the actuator, which has a moveable contact point.

Abstract translation: 一种开关装置的封装，其容纳具有可动接触点的致动器，并且其中精确地形成了与可动触点电连接或断开的固定触点。 本发明提供一种切换装置，其特征在于，包括：第一基板，具备将上表面和底面电连接的通孔，同时保持上表面与下表面之间的气密状态; 设置在第一基板上的第二基板，其中形成有容纳致动器的通孔; 以及设置在所述第二基板上并支撑所述致动器的第三基板，所述致动器具有可移动的接触点。

公开(公告)号：US20110241088A1

公开(公告)日：2011-10-06

申请号：US13075843

申请日：2011-03-30

Applicant: Yoshihiro SATO ,  Takehiko NOMURA ,  Nariaki IKEDA ,  Takuya KOKAWA ,  Masayuki IWAMI ,  Sadahiro KATO

Inventor： Yoshihiro SATO ,  Takehiko NOMURA ,  Nariaki IKEDA ,  Takuya KOKAWA ,  Masayuki IWAMI ,  Sadahiro KATO

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/306 ,  B82Y99/00 ,  B82Y40/00

CPC classification number: H01L29/0847 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7787

Abstract: A field effect transistor includes a high resistance layer on a substrate, a semiconductor operation layer that is formed on the high resistance layer and includes a channel layer that has the carbon concentration of not more than 1×1018 cm−3 and has the layer thickness of more than 10 nm and not more than 100 nm, a recess that is formed up to the inside of the channel layer in the semiconductor operation layer, source and drain electrodes that are formed on the semiconductor operation layer with the recess intervening therebetween, a gate insulating film that is formed on the semiconductor operation layer so as to cover the recess, and a gate electrode that is formed on the gate insulating film in the recess.

Abstract translation: 场效应晶体管包括在基板上的高电阻层，形成在高电阻层上并具有碳浓度不大于1×10 18 cm -3且具有层厚度的沟道层的半导体操作层 大于10nm且不大于100nm的凹槽，形成在半导体操作层中的沟道层内部的凹部，形成在半导体操作层上的沟槽间的沟槽间的沟槽间的沟槽， 栅极绝缘膜，其形成在半导体操作层上以覆盖凹部;以及栅电极，其形成在凹部中的栅极绝缘膜上。

公开(公告)号：US20100072523A1

公开(公告)日：2010-03-25

申请号：US12629508

申请日：2009-12-02

Applicant: Yoshihiro SATO ,  Hisashi Ogawa

Inventor： Yoshihiro SATO ,  Hisashi Ogawa

IPC: H01L27/092 ,  H01L21/8234

CPC classification number: H01L21/823807 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor device includes a first MIS transistor and a second MIS transistor. The first MIS transistor includes a first gate electrode includes a second metal film formed on a first gate insulating film, and an insulating film formed, extending over side surfaces of the first gate electrode and upper surfaces of regions located in the first active region laterally outside the first gate electrode. The second MIS transistor includes a second gate electrode including a first metal film formed on a second gate insulating film and a conductive film formed on the first metal film, and the insulating film formed, extending over side surfaces of the second gate electrode and upper surfaces of regions located in the second active region laterally outside the second gate electrode. The first and second metal films are made of different metal materials.

Abstract translation: 半导体器件包括第一MIS晶体管和第二MIS晶体管。 第一MIS晶体管包括：第一栅电极，包括形成在第一栅极绝缘膜上的第二金属膜和形成的绝缘膜，所述绝缘膜在第一栅电极的侧表面和位于第一有源区域的区域的上表面横向外侧延伸 第一栅电极。 第二MIS晶体管包括第二栅电极，其包括形成在第二栅极绝缘膜上的第一金属膜和形成在第一金属膜上的导电膜，并且形成在第二栅电极和上表面的侧表面上延伸的绝缘膜 位于第二有源区中的位于第二栅电极的横向外侧的区域。 第一和第二金属膜由不同的金属材料制成。

公开(公告)号：US20080283928A1

公开(公告)日：2008-11-20

申请号：US12028601

申请日：2008-02-08

Applicant: Yoshihiro SATO ,  Hisashi OGAWA

Inventor： Yoshihiro SATO ,  Hisashi OGAWA

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823857 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/092

Abstract: A semiconductor device comprises a first MIS transistor and a second MIS transistor. The first MIS transistor includes a first gate insulating film formed on a first active region, and a first gate electrode formed on the first gate insulating film. The second MIS transistor includes a second gate insulating film formed on a second active region and made of an insulating material different from that of the first gate insulating film, and a second gate electrode formed on the second gate insulating film. Upper regions of the first gate electrode and the second gate electrode are electrically connected to each other on the isolation region located between the first active region and the second active region, and lower regions thereof are separated from each other with a sidewall insulating film made of the same insulating material as that of the first gate insulating film being interposed therebetween.

Abstract translation: 半导体器件包括第一MIS晶体管和第二MIS晶体管。 第一MIS晶体管包括形成在第一有源区上的第一栅极绝缘膜和形成在第一栅极绝缘膜上的第一栅电极。 第二MIS晶体管包括形成在第二有源区上并由与第一栅极绝缘膜的绝缘材料不同的绝缘材料制成的第二栅极绝缘膜，以及形成在第二栅极绝缘膜上的第二栅电极。 第一栅极电极和第二栅电极的上部区域在位于第一有源区域和第二有源区域之间的隔离区域上彼此电连接，并且其下部区域由侧壁绝缘膜彼此分离，侧壁绝缘膜由 与第一栅极绝缘膜的绝缘材料相同的绝缘材料插入其间。

公开(公告)号：US20080179687A1

公开(公告)日：2008-07-31

申请号：US11950829

申请日：2007-12-05

Applicant: Yoshihiro SATO

Inventor： Yoshihiro SATO

IPC: H01L27/092 ,  H01L21/04

CPC classification number: H01L27/092 ,  H01L21/823835 ,  H01L21/823842

Abstract: A semiconductor device, wherein: the first MIS transistor includes a first fully-silicided gate electrode formed on a first gate insulating film and made of a first metal silicide film; and the second MIS transistor includes a second fully-silicided gate electrode formed on a second gate insulating film and made of a second metal silicide film whose silicide composition is different from that of the first metal silicide film. The semiconductor device further includes an L-shaped insulating film, the L-shaped insulating film being integral with the second gate insulating film and extending from a top of an isolation region formed between a first active region and a second active region of a semiconductor substrate along a side surface of the second fully-silicided gate electrode in a gate width direction; and the first fully-silicided gate electrode and the second fully-silicided gate electrode are electrically connected with each other.

Abstract translation: 一种半导体器件，其中：第一MIS晶体管包括形成在第一栅极绝缘膜上并由第一金属硅化物膜制成的第一全硅化物栅电极; 并且第二MIS晶体管包括形成在第二栅极绝缘膜上并由硅化物组成不同于第一金属硅化物膜的第二金属硅化物膜制成的第二全硅化物栅电极。 所述半导体器件还包括L形绝缘膜，所述L形绝缘膜与所述第二栅极绝缘膜成一体并从形成在半导体衬底的第一有源区和第二有源区之间的隔离区的顶部延伸 沿栅极宽度方向沿着第二全硅化物栅电极的侧表面; 并且第一全硅化物栅电极和第二全硅化栅电极彼此电连接。