公开(公告)号：US09716167B2

公开(公告)日：2017-07-25

申请号：US13032405

申请日：2011-02-22

Applicant: Yaojian Leng ,  Richard Wendell Foote, Jr. ,  Steven J. Adler

Inventor： Yaojian Leng ,  Richard Wendell Foote, Jr. ,  Steven J. Adler

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7809

Abstract: A trench DMOS transistor with a very low on-state drain-to-source resistance and a high gate-to-drain charge includes one or more floating islands that lie between the gate and drain to reduce the charge coupling between the gate and drain, and effectively lower the gate-to-drain capacitance.

公开(公告)号：US20120211826A1

公开(公告)日：2012-08-23

申请号：US13032405

申请日：2011-02-22

Applicant: Yaojian Leng ,  Richard Wendell Foote, JR. ,  Steven J. Adler

Inventor： Yaojian Leng ,  Richard Wendell Foote, JR. ,  Steven J. Adler

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7809

Abstract: A trench DMOS transistor with a very low on-state drain-to-source resistance and a high gate-to-drain charge includes one or more floating islands that lie between the gate and drain to reduce the charge coupling between the gate and drain, and effectively lower the gate-to-drain capacitance.

Abstract translation: 具有非常低的导通状态漏极至源极电阻和高栅极至漏极电荷的沟槽DMOS晶体管包括位于栅极和漏极之间的一个或多个浮置岛，以减少栅极和漏极之间的电荷耦合， 并有效降低栅 - 漏电容。

公开(公告)号：US07678657B1

公开(公告)日：2010-03-16

申请号：US11591850

申请日：2006-11-02

Applicant: Todd Patrick Thibeault ,  Steven J. Adler ,  Scott David Ruby

Inventor： Todd Patrick Thibeault ,  Steven J. Adler ,  Scott David Ruby

IPC: H01L21/44

CPC classification number: H01L21/8249

Abstract: A system and method are disclosed for manufacturing an emitter structure in a complementary bipolar complementary metal oxide semiconductor (CBiCMOS) transistor manufacturing process. A protective layer is formed over an emitter layer in a transistor structure and lateral portions of the protective layer and the emitter layer are etched to form an emitter structure. An oxide layer is then deposited over the transistor structure and an etchback process is performed to remove portions of the oxide layer from the top of the protective layer. A source/drain implant process is then performed to implant an extrinsic base region of the transistor. The protective layer protects the emitter structure from the implant process. Then the protective layer is removed from the emitter structure.

Abstract translation: 公开了用于制造互补双极互补金属氧化物半导体（CBiCMOS）晶体管制造工艺中的发射极结构的系统和方法。 在晶体管结构中的发射极层上形成保护层，并且保护层和发射极层的横向部分被蚀刻以形成发射极结构。 然后在晶体管结构上沉积氧化物层，并且执行回蚀工艺以从保护层的顶部去除氧化物层的部分。 然后执行源极/漏极注入工艺以注入晶体管的外部基极区域。 保护层保护发射器结构免受植入过程的影响。 然后从发射器结构去除保护层。

公开(公告)号：US08563345B2

公开(公告)日：2013-10-22

申请号：US13419216

申请日：2012-03-13

Applicant: Steven J. Adler ,  Peter Johnson ,  Gokhan Percin ,  Shahram Mostafazadeh

Inventor： Steven J. Adler ,  Peter Johnson ,  Gokhan Percin ,  Shahram Mostafazadeh

IPC: H01L29/72

CPC classification number: H01L27/1203 ,  B06B1/0292 ,  G01N29/2406 ,  H01L21/76898

Abstract: A method for forming a capacitive micromachined ultrasonic transducer (CMUT) includes forming multiple CMUT elements in a first semiconductor-on-insulator (SOI) structure. Each CMUT element includes multiple CMUT cells. The first SOI structure includes a first handle wafer, a first buried layer, and a first active layer. The method also includes forming a membrane over the CMUT elements and forming electrical contacts through the first handle wafer and the first buried layer. The electrical contacts are in electrical connection with the CMUT elements. The membrane could be formed by bonding a second SOI structure to the first SOI structure, where the second SOI structure includes a second handle wafer, a second buried layer, and a second active layer. The second handle wafer and the second buried layer can be removed, and the membrane includes the second active layer.

Abstract translation: 一种用于形成电容微加工超声换能器（CMUT）的方法包括在第一绝缘体上绝缘体（SOI）结构中形成多个CMUT元件。 每个CMUT元素包括多个CMUT单元。 第一SOI结构包括第一处理晶片，第一掩埋层和第一有源层。 该方法还包括在CMUT元件上形成膜并通过第一处理晶片和第一掩埋层形成电触点。 电触点与CMUT元件电连接。 可以通过将第二SOI结构结合到第一SOI结构来形成膜，其中第二SOI结构包括第二处理晶片，第二掩埋层和第二有源层。 可以去除第二处理晶片和第二掩埋层，并且膜包括第二有源层。

公开(公告)号：US20130001647A1

公开(公告)日：2013-01-03

申请号：US13170473

申请日：2011-06-28

Applicant: Steven J. Adler

Inventor： Steven J. Adler

IPC: H01L21/331 ,  H01L29/737 ,  H01L29/732

CPC classification number: H01L29/7317 ,  H01L21/84 ,  H01L27/1207 ,  H01L29/66242 ,  H01L29/66265 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7371

Abstract: In an embodiment, a bipolar transistor structure is formed on a silicon-on-insulator (SOI) structure that includes a semiconductor substrate, a buried oxide layer formed on the semiconductor substrate and a top silicon layer formed on the buried oxide layer. The bipolar transistor structure includes: an opening formed in the top silicon layer; an opening in the buried oxide layer beneath the opening in the top silicon layer, the opening in the buried oxide layer including a region that undercuts the opening in the top silicon layer at a side of the opening in the top silicon layer; conductive material having a first conductivity type formed in the opening in the buried oxide layer such that the conductive material includes a region that undercuts the top silicon layer at the side of the opening in the top silicon layer; isolation dielectric material formed in the top silicon layer over the region of conductive material that undercuts the top silicon layer to define a bipolar transistor collector region having the first conductivity type, the collector region being in contact with the region of conductive material; a bipolar transistor base region formed in contact with an upper surface of the collector region, the base region having a second conductivity type that is opposite the first conductivity type; and an emitter region formed in contact with the base region, the emitter region having the first conductivity type.

Abstract translation: 在一个实施例中，在包括半导体衬底，形成在半导体衬底上的掩埋氧化物层和形成在掩埋氧化物层上的顶部硅层的绝缘体上硅（SOI）结构上形成双极晶体管结构。 双极晶体管结构包括：形成在顶部硅层中的开口; 在顶层硅层开口下方的埋置氧化物层中的开口，掩埋氧化物层中的开口包括在顶部硅层中的开口侧的顶部硅层中的开口下切的区域; 具有第一导电类型的导电材料，形成在掩埋氧化物层中的开口中，使得导电材料包括在顶部硅层中的开口侧的顶部硅层下切的区域; 隔离电介质材料，形成在导电材料区域上的顶部硅层中，该导电材料区域覆盖顶部硅层以限定具有第一导电类型的双极晶体管集电极区域，该集电极区域与导电材料区域接触; 形成为与所述集电极区域的上表面接触的双极晶体管基极区域，所述基极区域具有与所述第一导电类型相反的第二导电类型; 以及与基极区域接触形成的发射极区域，发射极区域具有第一导电类型。

公开(公告)号：US5252848A

公开(公告)日：1993-10-12

申请号：US829190

申请日：1992-02-03

Applicant: Steven J. Adler ,  Robert B. Davies ,  Stephen J. Nugent ,  Hassan Pirastehfar

Inventor： Steven J. Adler ,  Robert B. Davies ,  Stephen J. Nugent ,  Hassan Pirastehfar

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/402 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/4175 ,  H01L29/41775 ,  H01L29/7813 ,  H01L29/7835

Abstract: A performance enhancing conductor (27) is employed to reduce a transistor's (10) on resistance and to also reduce the transistor's (10) parasitic gate to drain capacitance (32). The performance enhancing conductor (27) covers the transistor's (10) gate (22) and a portion of the drain region (18, 19) that is adjacent the transistor's channel (20). The performance enhancing conductor (27) is isolated from the gate (22) by an insulator (24, 26).

Abstract translation: 使用性能增强导体（27）来减小晶体管（10）导通电阻并且还将晶体管（10）的寄生栅极减小到漏极电容（32）。 性能增强导体（27）覆盖晶体管（10）栅极（22）和与晶体管通道（20）相邻的漏极区域（18,19）的一部分。 性能增强导体（27）通过绝缘体（24,26）与栅极（22）隔离。

公开(公告)号：US08324006B1

公开(公告)日：2012-12-04

申请号：US12589754

申请日：2009-10-28

Applicant: Steven J. Adler ,  Peter Johnson ,  Ira Wygant

Inventor： Steven J. Adler ,  Peter Johnson ,  Ira Wygant

IPC: H01H9/00 ,  H01L21/449

CPC classification number: B06B1/0292

Abstract: A method includes forming first isolation trenches in a first side of a first semiconductor-on-insulator (SOI) structure to electrically isolate multiple portions of the first SOI structure from each other. The method also includes bonding a second SOI structure to the first SOI structure to form multiple cavities between the SOI structures. The method further includes forming conductive plugs through a second side of the first SOI structure and forming second isolation trenches in the second side of the first SOI structure around the conductive plugs. In addition, the method includes removing portions of the second SOI structure to leave a membrane bonded to the first SOI structure. The isolated portions of the first SOI structure, the cavities, and the membrane form multiple capacitive micromachined ultrasonic transducer (CMUT) elements. Each CMUT element is formed in one of the isolated portions of the first SOI structure and includes multiple CMUT cells.

Abstract translation: 一种方法包括在第一绝缘体绝缘体（SOI）结构的第一侧中形成第一隔离沟槽，以将第一SOI结构的多个部分彼此电隔离。 该方法还包括将第二SOI结构接合到第一SOI结构以在SOI结构之间形成多个空腔。 该方法还包括通过第一SOI结构的第二侧形成导电插塞，并在导电插塞周围的第一SOI结构的第二侧形成第二隔离沟槽。 此外，该方法包括去除第二SOI结构的部分以留下结合到第一SOI结构的膜。 第一SOI结构，空腔和膜的隔离部分形成多个电容微加工超声换能器（CMUT）元件。 每个CMUT元件形成在第一SOI结构的隔离部分之一中，并且包括多个CMUT单元。

公开(公告)号：US07910447B1

公开(公告)日：2011-03-22

申请号：US11803539

申请日：2007-05-15

Applicant: Mingwei Xu ,  Steven J. Adler

Inventor： Mingwei Xu ,  Steven J. Adler

IPC: H01L21/8222

CPC classification number: H01L29/0821 ,  H01L29/66287 ,  H01L29/7322

Abstract: A system and method are disclosed for providing a self aligned bipolar transistor using a simplified sacrificial nitride emitter. An active region of a transistor is formed and a silicon nitride sacrificial emitter is formed above the active region of the transistor. Then a physical vapor deposition oxide layer is deposited over the silicon nitride sacrificial emitter using a physical vapor deposition process. The physical vapor deposition oxide layer is then etched away from the side walls of the sacrificial emitter. The sacrificial emitter is then etched away to form an emitter window. Then a polysilicon emitter structure is formed in the emitter window. The self aligned bipolar transistor architecture of the invention is compatible with BiCMOS technology.

Abstract translation: 公开了一种使用简化的牺牲氮化物发射器提供自对准双极晶体管的系统和方法。 形成晶体管的有源区，并且在晶体管的有源区上方形成氮化硅牺牲发射极。 然后使用物理气相沉积工艺在氮化硅牺牲发射体上沉积物理气相沉积氧化物层。 物理气相沉积氧化物层然后从牺牲发射体的侧壁蚀刻掉。 然后将牺牲发射器蚀刻掉以形成发射器窗口。 然后在发射器窗口中形成多晶硅发射极结构。 本发明的自对准双极晶体管结构与BiCMOS技术兼容。

公开(公告)号：US07781295B1

公开(公告)日：2010-08-24

申请号：US11486967

申请日：2006-07-13

Applicant: Jamal Ramdani ,  Craig Printy ,  Steven J. Adler ,  Andre P. Labonte

Inventor： Jamal Ramdani ,  Craig Printy ,  Steven J. Adler ,  Andre P. Labonte

IPC: H01L21/331

CPC classification number: H01L29/7371 ,  H01L29/66287

Abstract: A system and method is disclosed for manufacturing a bipolar junction transistor that comprises an emitter/base layer that is formed by a single deposition process. In one advantageous embodiment of the invention the emitter/base layer comprises an emitter layer that comprises an epitaxially grown mono-silicon emitter. The epitaxially grown mono-silicon emitter significantly reduces the electrical resistivity of the emitter. A non-dopant impurity such as germanium is added to the base layer to endpoint a dry plasma etch process that is applied to etch the emitter/base layer.

Abstract translation: 公开了用于制造双极结型晶体管的系统和方法，该双极结型晶体管包括通过单个沉积工艺形成的发射极/基极层。 在本发明的一个有利实施例中，发射极/基极层包括包含外延生长单晶硅发射极的发射极层。 外延生长的单硅发射极显着降低了发射极的电阻率。 将诸如锗的非掺杂杂质添加到基底层中，以终止用于蚀刻发射极/基底层的干等离子体蚀刻工艺。

公开(公告)号：US20120187508A1

公开(公告)日：2012-07-26

申请号：US13419216

申请日：2012-03-13

Applicant: Steven J. Adler ,  Peter Johnson ,  Gokhan Percin ,  Shahram Mostafazadeh

Inventor： Steven J. Adler ,  Peter Johnson ,  Gokhan Percin ,  Shahram Mostafazadeh

IPC: H01L29/84 ,  H01L21/50

CPC classification number: H01L27/1203 ,  B06B1/0292 ,  G01N29/2406 ,  H01L21/76898

Abstract: A method for forming a capacitive micromachined ultrasonic transducer (CMUT) includes forming multiple CMUT elements in a first semiconductor-on-insulator (SOI) structure. Each CMUT element includes multiple CMUT cells. The first SOI structure includes a first handle wafer, a first buried layer, and a first active layer. The method also includes forming a membrane over the CMUT elements and forming electrical contacts through the first handle wafer and the first buried layer. The electrical contacts are in electrical connection with the CMUT elements. The membrane could be formed by bonding a second SOI structure to the first SOI structure, where the second SOI structure includes a second handle wafer, a second buried layer, and a second active layer. The second handle wafer and the second buried layer can be removed, and the membrane includes the second active layer.

Abstract translation: 一种用于形成电容微加工超声换能器（CMUT）的方法包括在第一绝缘体上绝缘体（SOI）结构中形成多个CMUT元件。 每个CMUT元素包括多个CMUT单元。 第一SOI结构包括第一处理晶片，第一掩埋层和第一有源层。 该方法还包括在CMUT元件上形成膜并通过第一处理晶片和第一掩埋层形成电触点。 电触点与CMUT元件电连接。 可以通过将第二SOI结构结合到第一SOI结构来形成膜，其中第二SOI结构包括第二处理晶片，第二掩埋层和第二有源层。 可以去除第二处理晶片和第二掩埋层，并且膜包括第二有源层。