公开(公告)号：US20130178055A1

公开(公告)日：2013-07-11

申请号：US13345879

申请日：2012-01-09

Applicant: Andre P. LaBonte ,  Phillip L. Jones

Inventor： Andre P. LaBonte ,  Phillip L. Jones

IPC: H01L21/28 ,  H01L21/283

CPC classification number: H01L29/66545 ,  H01L21/28114 ,  H01L21/32134 ,  H01L21/32135 ,  H01L29/42376 ,  H01L29/7833

Abstract: Disclosed herein are methods of forming a replacement gate structure having a reentrant profile. In one example, the method includes forming a layer of material for a sacrificial gate electrode, wherein the layer of material includes at least one impurity that changes the etch rate of the layer of material as compared to an etch rate for the layer of material without the impurity, and wherein a concentration of the at least one impurity varies along a direction that corresponds to a thickness of the layer of material, and performing another etching process on the layer of material to define a sacrificial gate electrode. The method concludes with the steps of performing another etching process to remove the sacrificial gate electrode so as to at least partially define a gate opening in a layer of insulating material and forming a replacement gate structure in the gate opening.

Abstract translation: 本文公开了形成具有折返轮廓的替换栅极结构的方法。 在一个示例中，该方法包括形成用于牺牲栅极电极的材料层，其中该材料层包括改变材料层的蚀刻速率的至少一种杂质，与该材料层的蚀刻速率相比较，没有 杂质，并且其中所述至少一种杂质的浓度沿着对应于所述材料层的厚度的方向变化，并且对所述材料层进行另一蚀刻工艺以限定牺牲栅电极。 该方法的结论是执行另一蚀刻工艺以去除牺牲栅电极，以便至少部分地限定绝缘材料层中的栅极开口并在栅极开口中形成替代栅极结构。

公开(公告)号：US08007675B1

公开(公告)日：2011-08-30

申请号：US11178557

申请日：2005-07-11

Applicant: Andre P. Labonte ,  Craig Richard Printy

Inventor： Andre P. Labonte ,  Craig Richard Printy

IPC: C03C25/68

CPC classification number: H01L22/26 ,  H01L21/3065 ,  H01L22/12

Abstract: A system and method is disclosed that terminates an etch process of a semiconductor crystal material at a precisely located depth. The semiconductor crystal is made of a first material and has a buried layer of a second material that is stoichiometrically different than the first material. The buried layer is located at a depth in the first material at which it is desired to terminate the etch process. During the etch process an optical emission spectrum of the first material is monitored. The intensity of the spectrum decreases when the etch process reaches the second material of the buried layer. The etch process is terminated when the decrease in spectrum intensity is detected.

Abstract translation: 公开了一种在精确定位的深度处终止半导体晶体材料的蚀刻工艺的系统和方法。 半导体晶体由第一材料制成，并且具有与第一材料化学计量不同的第二材料的掩埋层。 掩埋层位于第一材料的深度处，期望终止蚀刻工艺。 在蚀刻工艺期间，监测第一材料的光发射光谱。 当蚀刻工艺到达掩埋层的第二材料时，光谱的强度降低。 当检测到光谱强度的降低时，蚀刻过程终止。

公开(公告)号：US20110042778A1

公开(公告)日：2011-02-24

申请号：US12917332

申请日：2010-11-01

Applicant: Craig Printy ,  Andre P. Labonte ,  Jamal Ramdani

Inventor： Craig Printy ,  Andre P. Labonte ,  Jamal Ramdani

IPC: H01L29/06

CPC classification number: H01L27/1207 ,  H01L21/76264

Abstract: One or more trenches can be formed around a first portion of a semiconductor substrate, and an insulating layer can be formed under the first portion of the semiconductor substrate. The one or more trenches and the insulating layer electrically isolate the first portion of the substrate from a second portion of the substrate. The insulating layer can be formed by forming a buried layer in the substrate, such as a silicon germanium layer in a silicon substrate. One or more first trenches through the substrate to the buried layer can be formed, and open spaces can be formed in the buried layer (such as by using an etch selective to silicon germanium over silicon). The one or more first trenches and the open spaces can optionally be filled with insulative material(s). One or more second trenches can be formed and filled to isolate the first portion of the substrate.

Abstract translation: 可以在半导体衬底的第一部分周围形成一个或多个沟槽，并且可以在半导体衬底的第一部分之下形成绝缘层。 一个或多个沟槽和绝缘层将衬底的第一部分与衬底的第二部分电隔离。 可以通过在硅衬底中的诸如硅锗层的衬底中形成掩埋层来形成绝缘层。 可以形成通过衬底到掩埋层的一个或多个第一沟槽，并且可以在掩埋层中形成开放空间（例如通过使用对硅上的硅锗的选择性蚀刻）。 一个或多个第一沟槽和开放空间可以可选地用绝缘材料填充。 可以形成并填充一个或多个第二沟槽以隔离衬底的第一部分。

公开(公告)号：US08502296B1

公开(公告)日：2013-08-06

申请号：US12217539

申请日：2008-07-07

Applicant: Andre P. Labonte ,  Jiankang Bu ,  Mark Rathmell

Inventor： Andre P. Labonte ,  Jiankang Bu ,  Mark Rathmell

IPC: H01L29/788

CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method includes forming at least one control gate over a semiconductor substrate. The method also includes depositing a layer of conductive material over the at least one control gate and the semiconductor substrate. The method further includes etching the layer of conductive material to form multiple spacers adjacent to the at least one control gate, where at least one of the spacers forms a floating gate in at least one memory cell. Two spacers could be formed adjacent to the at least one control gate, and one of the spacers could be etched so that a single memory cell includes the control gate and the remaining spacer. Also, two spacers could be formed adjacent to the at least one control gate, and the at least one control gate could be etched and separated to form multiple control gates associated with different memory cells.

Abstract translation: 一种方法包括在半导体衬底上形成至少一个控制栅极。 该方法还包括在至少一个控制栅极和半导体衬底上沉积一层导电材料。 该方法还包括蚀刻导电材料层以形成与至少一个控制栅极相邻的多个间隔区，其中至少一个间隔物在至少一个存储单元中形成浮置栅极。 可以在至少一个控制栅极附近形成两个间隔物，并且可以蚀刻一个间隔物，使得单个存储器单元包括控制栅极和剩余的间隔物。 而且，可以与至少一个控制栅极相邻地形成两个间隔物，并且可以蚀刻和分离至少一个控制栅极以形成与不同存储器单元相关联的多个控制栅极。

公开(公告)号：US07968418B1

公开(公告)日：2011-06-28

申请号：US11786002

申请日：2007-04-10

Applicant: Andre P. Labonte ,  Todd P. Thibeault

Inventor： Andre P. Labonte ,  Todd P. Thibeault

IPC: H01L21/331

CPC classification number: H01L21/76232

Abstract: An isolation trench structure includes both a deep trench isolation (DTI) trench and a shallow trench isolation (STI) trench. The DTI trench can be formed by etching a deeper, narrower trench in a substrate and filling the deeper trench with one or more materials (such as an oxide). The STI trench can be formed by etching a shallower, wider trench in the substrate and filling the shallower trench with one or more materials (such as an oxide). The STI trench surrounds a portion of the DTI trench, such as by completely encircling an upper portion of the DTI trench. The DTI and STI trenches are filled during different operations, and the DTI and STI trenches can be filled with the same material(s) or with different material(s).

Abstract translation: 隔离沟槽结构包括深沟槽隔离（DTI）沟槽和浅沟槽隔离（STI）沟槽。 可以通过蚀刻衬底中更深更窄的沟槽并用一种或多种材料（例如氧化物）填充较深的沟槽来形成DTI沟槽。 可以通过蚀刻衬底中较浅的较宽沟槽并用一种或多种材料（例如氧化物）填充较浅的沟槽来形成STI沟槽。 STI沟槽围绕DTI沟槽的一部分，例如通过完全环绕DTI沟槽的上部。 DTI和STI沟槽在不同的操作期间被填充，并且DTI和STI沟槽可以用相同的材​​料或不同的材料填充。

公开(公告)号：US07781295B1

公开(公告)日：2010-08-24

申请号：US11486967

申请日：2006-07-13

Applicant: Jamal Ramdani ,  Craig Printy ,  Steven J. Adler ,  Andre P. Labonte

Inventor： Jamal Ramdani ,  Craig Printy ,  Steven J. Adler ,  Andre P. Labonte

IPC: H01L21/331

CPC classification number: H01L29/7371 ,  H01L29/66287

Abstract: A system and method is disclosed for manufacturing a bipolar junction transistor that comprises an emitter/base layer that is formed by a single deposition process. In one advantageous embodiment of the invention the emitter/base layer comprises an emitter layer that comprises an epitaxially grown mono-silicon emitter. The epitaxially grown mono-silicon emitter significantly reduces the electrical resistivity of the emitter. A non-dopant impurity such as germanium is added to the base layer to endpoint a dry plasma etch process that is applied to etch the emitter/base layer.

Abstract translation: 公开了用于制造双极结型晶体管的系统和方法，该双极结型晶体管包括通过单个沉积工艺形成的发射极/基极层。 在本发明的一个有利实施例中，发射极/基极层包括包含外延生长单晶硅发射极的发射极层。 外延生长的单硅发射极显着降低了发射极的电阻率。 将诸如锗的非掺杂杂质添加到基底层中，以终止用于蚀刻发射极/基底层的干等离子体蚀刻工艺。

公开(公告)号：US07829429B1

公开(公告)日：2010-11-09

申请号：US11901688

申请日：2007-09-18

Applicant: Craig Printy ,  Andre P. Labonte ,  Jamal Ramdani

Inventor： Craig Printy ,  Andre P. Labonte ,  Jamal Ramdani

IPC: H01L21/76 ,  H01L29/00

CPC classification number: H01L27/1207 ,  H01L21/76264

Abstract: One or more trenches can be formed around a first portion of a semiconductor substrate, and an insulating layer can be formed under the first portion of the semiconductor substrate. The one or more trenches and the insulating layer electrically isolate the first portion of the substrate from a second portion of the substrate. The insulating layer can be formed by forming a buried layer in the substrate, such as a silicon germanium layer in a silicon substrate. One or more first trenches through the substrate to the buried layer can be formed, and open spaces can be formed in the buried layer (such as by using an etch selective to silicon germanium over silicon). The one or more first trenches and the open spaces can optionally be filled with insulative material(s). One or more second trenches can be formed and filled to isolate the first portion of the substrate.

Abstract translation: 可以在半导体衬底的第一部分周围形成一个或多个沟槽，并且可以在半导体衬底的第一部分之下形成绝缘层。 一个或多个沟槽和绝缘层将衬底的第一部分与衬底的第二部分电隔离。 可以通过在硅衬底中的诸如硅锗层的衬底中形成掩埋层来形成绝缘层。 可以形成通过衬底到掩埋层的一个或多个第一沟槽，并且可以在掩埋层中形成开放空间（例如通过使用对硅上的硅锗的选择性蚀刻）。 一个或多个第一沟槽和开放空间可以可选地用绝缘材料填充。 可以形成并填充一个或多个第二沟槽以隔离衬底的第一部分。