公开(公告)号：US20110024910A1

公开(公告)日：2011-02-03

申请号：US12904988

申请日：2010-10-14

Applicant: Shahram MOSTAFAZADEH ,  Viraj A. PATWARDHAN

Inventor： Shahram MOSTAFAZADEH ,  Viraj A. PATWARDHAN

IPC: H01L23/492 ,  H01L21/768

CPC classification number: H01L24/03 ,  H01L22/32 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05016 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Improved protective metallization arrangements are described that are particularly useful in bumped copper-top type semiconductor chips. In one aspect of the invention, the semiconductor device includes integrated circuits and has a top wafer fabrication passivation layer. A plurality of I/O pads are exposed through contact pad openings formed in the top wafer fabrication passivation layer. A patterned copper layer is formed over the top wafer fabrication passivation layer. The patterned copper layer is electrically coupled to the contact pads through the contact pad openings. A metallic barrier layer is provided between the contact pads and the patterned copper layer. A titanium metallization layer overlies at least portions of the patterned copper layer and preferably cooperates with the barrier layer to envelop the copper layer in the regions of the contact pads. A first aluminum metallization layer overlies at least portions of the titanium metallization layer. An electrically insulating protective layer overlies the first aluminum metallization layer and the top wafer fabrication passivation layer. The protective layer is preferably formed from an organic material and includes a plurality of contact openings. Underbump metallization stacks are formed in the contact openings. Each underbump metallization stack is electrically connected to the first aluminum metallization layer through its associated contact opening in the protective layer. Solder bumps are preferably then adhered to the underbump metallization stacks.

Abstract translation: 描述了改进的保护性金属化布置，其在凸起的铜顶型半导体芯片中特别有用。 在本发明的一个方面，半导体器件包括集成电路并具有顶部晶片制造钝化层。 多个I / O焊盘通过形成在顶部晶片制造钝化层中的接触焊盘开口露出。 在顶部晶片制造钝化层上形成图案化的铜层。 图案化的铜层通过接触焊盘开口电耦合到接触焊盘。 金属阻挡层设置在接触焊盘和图案化铜层之间。 钛金属化层覆盖图案化的铜层的至少部分，并且优选与阻挡层配合以包围接触焊盘区域中的铜层。 第一铝金属化层覆盖钛金属化层的至少一部分。 电绝缘保护层覆盖在第一铝金属化层和顶部晶片制造钝化层之间。 保护层优选由有机材料形成并且包括多个接触开口。 底部金属化叠层形成在接触开口中。 每个底部浸渍金属化叠层通过其保护层中的相关接触开口与第一铝金属化层电连接。 然后优选将焊料凸块粘附到下凸点金属化叠层。

公开(公告)号：US07144800B2

公开(公告)日：2006-12-05

申请号：US10890896

申请日：2004-07-13

Applicant: Shahram Mostafazadeh ,  Joseph O. Smith

Inventor： Shahram Mostafazadeh ,  Joseph O. Smith

IPC: H01L21/00 ,  H01L23/495 ,  H01L23/02 ,  H01L29/40

CPC classification number: H01L23/3107 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L2223/54493 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0401

Abstract: Multichip packages and methods for making same. The present invention generally allows for either the back of a flipchip, the back of a mother die, or both to be exposed in a multichip package. When the mother die is connected to the package contacts, the back of the flip chip is higher than the electrical connections. Accordingly, the back of the flip chip can be exposed. Furthermore, if a temporary tape substrate is used with a leadframe panel that does not have a die attach pad, the package can be even thinner. Once the temporary tape substrate is removed, both the back of the flipchip and the back of the mother die will be exposed from the encapsulant.

Abstract translation: Multichip包和其制作方法。 本发明通常允许倒装芯片的背面，母模的背面或两者都暴露在多芯片封装中。 当母体裸片连接到封装触点时，倒装芯片的背面高于电气连接。 因此，可以暴露倒装芯片的背面。 此外，如果临时带基板与不具有管芯附接垫的引线框面板一起使用，则封装可以更薄。 一旦临时的胶带基板被去除，倒装芯片的背面和母模的背面都将从密封剂暴露出来。

公开(公告)号：US06936929B1

公开(公告)日：2005-08-30

申请号：US10391160

申请日：2003-03-17

Applicant: Shahram Mostafazadeh ,  Joseph O. Smith

Inventor： Shahram Mostafazadeh ,  Joseph O. Smith

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L29/40

CPC classification number: H01L23/3107 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L2223/54493 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0401

Abstract: Multichip packages and methods for making same. The present invention generally allows for either the back of a flipchip, the back of a mother die, or both to be exposed in a multichip package. When the mother die is connected to the package contacts, the back of the flip chip is higher than the electrical connections. Accordingly, the back of the flip chip can be exposed. Furthermore, if a temporary tape substrate is used with a leadframe panel that does not have a die attach pad, the package can be even thinner. Once the temporary tape substrate is removed, both the back of the flipchip and the back of the mother die will be exposed from the encapsulant.

Abstract translation: Multichip包和其制作方法。 本发明通常允许倒装芯片的背面，母模的背面或两者都暴露在多芯片封装中。 当母体裸片连接到封装触点时，倒装芯片的背面高于电气连接。 因此，可以暴露倒装芯片的背面。 此外，如果临时带基板与不具有管芯附接垫的引线框面板一起使用，则封装可以更薄。 一旦临时的胶带基板被去除，倒装芯片的背面和母模的背面都将从密封剂暴露出来。

公开(公告)号：US06888228B1

公开(公告)日：2005-05-03

申请号：US09625071

申请日：2000-07-25

Applicant: Shahram Mostafazadeh ,  Joseph O. Smith

Inventor： Shahram Mostafazadeh ,  Joseph O. Smith

IPC: H01L21/56 ,  H01L21/68 ,  H01L23/24 ,  H01L23/495

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L23/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: In one aspect of the invention, a lead frame panel suitable for use in packaging an array of integrated circuits is described. The lead frame panel includes a matrix of tie bars that extend in substantially perpendicular rows and columns to define a two dimensional array of immediately adjacent device areas separated only by the tie bars. Each device area is suitable for use in an independent integrated circuit package and includes a die attach pad and a plurality of conductive contacts. In another aspect of the invention, a panel assembly suitable for use in simultaneously packaging a multiplicity of integrated circuits is described. The panel assembly includes a lead frame panel formed from a conductive sheet. The lead frame panel is patterned to define at least one two dimensional array of adjacent device areas. Each device area is suitable for use as part of an independent integrated circuit package and including a die and a plurality of contacts positioned around and electrically connected to the die. A molded cap is also provided that substantially uniformly covers a two dimensional array of adjacent device areas while leaving bottom surfaces of the conductive contacts exposed to facilitate electrical connection to external components. The encapsulation material that forms the molded cap is exposed at a bottom surface of the panel of integrated circuits to physically isolate the contacts.

Abstract translation: 在本发明的一个方面，描述了适用于封装集成电路阵列的引线框架面板。 引线框架面板包括一系列连接杆，其基本垂直的行和列延伸，以限定仅由连接杆分离的紧邻设备区域的二维阵列。 每个器件区域适用于独立的集成电路封装，并且包括管芯附接焊盘和多个导电触点。 在本发明的另一方面，描述了适用于同时封装多个集成电路的面板组件。 面板组件包括由导电片形成的引线框架面板。 图案化引线框架面板以限定相邻设备区域的至少一个二维阵列。 每个器件区域适合用作独立集成电路封装的一部分，并且包括管芯和定位在芯片周围并电连接到管芯的多个触点。 还提供了模制盖，其基本上均匀地覆盖相邻设备区域的二维阵列，同时使导电触头的底表面暴露以促进与外部组件的电连接。 形成模制帽的封装材料暴露在集成电路板的底表面以物理地隔离触点。

公开(公告)号：US06710246B1

公开(公告)日：2004-03-23

申请号：US10211450

申请日：2002-08-02

Applicant: Shahram Mostafazadeh ,  Joseph O. Smith

Inventor： Shahram Mostafazadeh ,  Joseph O. Smith

IPC: H01L2302

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A package, a method of making and a method of assembly of packages for semiconductor chips are disclosed. The package includes a die attach pad on which a semiconductor die is mounted. A lead is electrically connected to the semiconductor die which is encapsulated in packaging material. The lead is exposed at opposed sides of the package. Exposing the lead on both sides of the package allows the package to be stacked or assembled so that the leads of adjacent pairs of packages are in electrical contact. Making the semiconductor packages includes forming a piece of electrically conductive material into a die attach pad and at least one lead associated with the die attach pad. A semiconductor die is mounted on the die attach pad and an electrical connection is made between the semiconductor die and the lead. The package is formed by encapsulation with the lead exposed on opposite sides of the package.

Abstract translation: 公开了一种用于半导体芯片的封装，封装方法和组装方法。 该封装包括其上安装有半导体管芯的管芯附接焊盘。 引线与封装在封装材料中的半导体管芯电连接。 引线暴露在封装的相对两侧。 在封装的两侧露出引线允许封装被堆叠或组装，使得相邻封装对的引线电接触。 制造半导体封装包括将一块导电材料形成到管芯附接焊盘和与管芯附接焊盘相关联的至少一个引线。 半导体管芯安装在管芯附接焊盘上，并且在半导体管芯和引线之间形成电连接。 封装通过封装形成，引线暴露在封装的相对两侧。

公开(公告)号：US06689640B1

公开(公告)日：2004-02-10

申请号：US09698736

申请日：2000-10-26

Applicant: Shahram Mostafazadeh

Inventor： Shahram Mostafazadeh

IPC: H01L2144

CPC classification number: H01L23/3114 ,  H01L21/4832 ,  H01L21/561 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: An integrated circuit package with lead fingers with a footprint on the order of the integrated circuit footprint is provided. A lead frame may be made from a metal sheet, which may be stamped or etched. The lead frame provides a plurality of posts and a connecting sheet connecting the plurality of posts. Dice are adhesively mounted to the plurality of posts. The dice have a conductive side with a plurality of conducting pads where each conducting pad is electrically and mechanically connected to a post. An encapsulating material is placed over the dice and lead frame, with the connecting sheet keeping the encapsulating material on one side of the lead frame. Parts of the connecting sheet are then removed, electrically isolating the posts. The integrated circuit packages formed by the encapsulated dice and leads may be tested as a panel, before the integrated circuit packages are singulated.

Abstract translation: 提供了具有引脚的集成电路封装，其具有集成电路占用空间的占位面积。 引线框架可以由可以冲压或蚀刻的金属板制成。 引线框架提供多个柱和连接多个柱的连接片。 骰子粘合地安装到多个柱。 骰子具有导电侧，具有多个导电垫，其中每个导电垫电连接和机械地连接到柱。 将封装材料放置在骰子和引线框架上方，连接片将封装材料保持在引线框架的一侧。 然后拆下连接片的部分，电隔离柱。 在封装集成电路封装被分割之前，封装裸片和引线形成的集成电路封装可以作为面板进行测试。

公开(公告)号：US6054772A

公开(公告)日：2000-04-25

申请号：US70111

申请日：1998-04-29

Applicant: Shahram Mostafazadeh ,  Joseph O. Smith

Inventor： Shahram Mostafazadeh ,  Joseph O. Smith

IPC: H01L23/31 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/3107 ,  H01L2224/1134 ,  H01L2224/94

Abstract: An improved wafer based packaging arrangement for integrated circuits is disclosed. In one aspect of the invention, external contacts are formed for the packaged integrated circuits by contact studs formed from bonding wires. One end of each contact studs is ball bonded to an associated wafer bond pad. An elongated portion of each wire (contact stud) extends outward the wafer surface and terminates at a second end that forms an external contact. Filling material surrounds a significant portion of the contact studs to hold the studs in place but leaves at least a portion of the second ends exposed to form external contacts. In some embodiments, the external contacts are substantially coplanar with the surface of the filling material, while in others, a protrusion beyond the filling material surface is left to form a contact bump. The wafers are eventually diced to form discrete packaged integrated circuits having external contacts formed by the contact studs.

Abstract translation: 公开了用于集成电路的改进的基于晶片的封装装置。 在本发明的一个方面，通过由接合线形成的接触柱形成用于封装的集成电路的外部接触。 每个接触螺柱的一端球焊接到相关联的晶片接合焊盘。 每个线（接触柱）的细长部分向外延伸晶片表面，并终止于形成外部接触的第二端。 填充材料围绕接触柱的重要部分以将螺柱保持在适当的位置，但是将第二端的至少一部分暴露以形成外部接触。 在一些实施例中，外部触点与填充材料的表面基本上共面，而在另一些实施例中，留下超过填充材料表面的突起形成接触凸块。 最终切割晶片以形成具有由接触柱形成的外部触头的分立的封装集成电路。

公开(公告)号：US20120187508A1

公开(公告)日：2012-07-26

申请号：US13419216

申请日：2012-03-13

Applicant: Steven J. Adler ,  Peter Johnson ,  Gokhan Percin ,  Shahram Mostafazadeh

Inventor： Steven J. Adler ,  Peter Johnson ,  Gokhan Percin ,  Shahram Mostafazadeh

IPC: H01L29/84 ,  H01L21/50

CPC classification number: H01L27/1203 ,  B06B1/0292 ,  G01N29/2406 ,  H01L21/76898

Abstract: A method for forming a capacitive micromachined ultrasonic transducer (CMUT) includes forming multiple CMUT elements in a first semiconductor-on-insulator (SOI) structure. Each CMUT element includes multiple CMUT cells. The first SOI structure includes a first handle wafer, a first buried layer, and a first active layer. The method also includes forming a membrane over the CMUT elements and forming electrical contacts through the first handle wafer and the first buried layer. The electrical contacts are in electrical connection with the CMUT elements. The membrane could be formed by bonding a second SOI structure to the first SOI structure, where the second SOI structure includes a second handle wafer, a second buried layer, and a second active layer. The second handle wafer and the second buried layer can be removed, and the membrane includes the second active layer.

Abstract translation: 一种用于形成电容微加工超声换能器（CMUT）的方法包括在第一绝缘体上绝缘体（SOI）结构中形成多个CMUT元件。 每个CMUT元素包括多个CMUT单元。 第一SOI结构包括第一处理晶片，第一掩埋层和第一有源层。 该方法还包括在CMUT元件上形成膜并通过第一处理晶片和第一掩埋层形成电触点。 电触点与CMUT元件电连接。 可以通过将第二SOI结构结合到第一SOI结构来形成膜，其中第二SOI结构包括第二处理晶片，第二掩埋层和第二有源层。 可以去除第二处理晶片和第二掩埋层，并且膜包括第二有源层。

公开(公告)号：US07468288B1

公开(公告)日：2008-12-23

申请号：US11481699

申请日：2006-07-05

Applicant: Shahram Mostafazadeh ,  Joseph O. Smith

Inventor： Shahram Mostafazadeh ,  Joseph O. Smith

IPC: H01L21/00 ,  H01L21/44

CPC classification number: H01L31/0203 ,  H01L23/481 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L24/81 ,  H01L27/14618 ,  H01L33/62 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/16195 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: The invention includes a die-level opto-electronic device with a semiconductor die and a photonic device including a conductive structure formed in the die away from the edges of the die. The conductive structure is electrically connected to the photonic device. The device also includes an optically transparent laminate attached to overlay the photonic device. The invention also comprises a semiconductor wafer with a plurality of photonic devices exposed on a first surface and a plurality of conductive structures being exposed on a second surface opposing the first surface. The conductive structures are electrically connected to the photonic devices which are overlaid with an optically transparent laminate. The invention further includes methods of forming die-level opto-electronic devices and semiconductor wafers.

Abstract translation: 本发明包括具有半导体管芯的管芯级光电器件和包括在模具中形成的导电结构的光子器件，远离管芯的边缘。 导电结构电连接到光子器件。 该装置还包括附着以覆盖光子装置的光学透明层压体。 本发明还包括具有暴露在第一表面上的多个光子器件的半导体晶片，并且在与第一表面相对的第二表面上露出多个导电结构。 导电结构电连接到用光学透明层压体覆盖的光子器件。 本发明还包括形成管芯级光电器件和半导体晶片的方法。

公开(公告)号：USRE39854E1

公开(公告)日：2007-09-25

申请号：US10260044

申请日：2002-09-27

Applicant: Shahram Mostafazadeh ,  Joseph O. Smith

Inventor： Shahram Mostafazadeh ,  Joseph O. Smith

IPC: H01L23/495

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L23/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A method for producing chip scale IC packages includes the step of mounting a lead frame panel on a temporary support fixture in order to provide support and protection during the manufacturing process. An embodiment of the temporary support fixture includes a sheet of sticky tape secured to a rigid frame. The rigid frame maintains tension in the sheet of sticky tape to provide a stable surface to which the lead frame panel can be affixed. Installation of IC chips and encapsulation in protective casings is performed as in conventional IC package manufacturing. If encapsulant material is to be dispensed over the IC chips, an encapsulant dam can be formed around the lead frame panel to contain the flow of encapsulant material. The temporary support fixture can be used in any IC package manufacturing process in which lead frames require supplemental support.

Abstract translation: 制造芯片级IC封装的方法包括将引线框架面板安装在临时支撑固定装置上以便在制造过程中提供支撑和保护的步骤。 临时支撑固定装置的一个实施例包括固定到刚性框架的粘性片材片。 刚性框架保持粘性胶带中的张力，以提供稳定的表面，引线框架面板可以固定到该表面上。 IC芯片的安装和保护套管中的封装按照传统的IC封装制造进行。 如果将密封剂材料分配在IC芯片上，则可以在引线框架板周围形成密封剂坝以容纳密封材料的流动。 临时支撑夹具可用于任何IC封装制造工艺，其中引线框架需要补充支撑。