公开(公告)号：US4961097A

公开(公告)日：1990-10-02

申请号：US710781

申请日：1985-03-11

Applicant: Hassan Pirastehfar ,  George C. Onodera ,  Waisiu Law ,  David M. Heminger

Inventor： Hassan Pirastehfar ,  George C. Onodera ,  Waisiu Law ,  David M. Heminger

IPC: H01L27/14 ,  H01L21/762 ,  H01L31/0352 ,  H01L31/10 ,  H01L31/103 ,  H01L31/18

CPC classification number: H01L31/1804 ,  H01L21/76297 ,  H01L31/03529 ,  H01L31/103 ,  Y02E10/547 ,  Y02P70/521

Abstract: An improved photo detector is provided by forming a tub of monocrystalline semiconductor material surrounded by a layer of monocrystalline material of opposite conductivity type. The improved structure is manufactured by means of a modified DIC process. The device may by made deep enough to absorb a large portion of the incident radiation near the PN junction without sacrificing a large number of photo-generated carriers to recombination.

Abstract translation: 通过形成由相反导电类型的单晶材料层包围的单晶半导体材料桶来提供改进的光电检测器。 改进的结构通过改进的DIC工艺制造。 该器件可以通过制造得足够深以吸收PN结附近的大部分入射辐射而不牺牲大量光生载流子进行复合。

公开(公告)号：US5252848A

公开(公告)日：1993-10-12

申请号：US829190

申请日：1992-02-03

Applicant: Steven J. Adler ,  Robert B. Davies ,  Stephen J. Nugent ,  Hassan Pirastehfar

Inventor： Steven J. Adler ,  Robert B. Davies ,  Stephen J. Nugent ,  Hassan Pirastehfar

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/402 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/4175 ,  H01L29/41775 ,  H01L29/7813 ,  H01L29/7835

Abstract: A performance enhancing conductor (27) is employed to reduce a transistor's (10) on resistance and to also reduce the transistor's (10) parasitic gate to drain capacitance (32). The performance enhancing conductor (27) covers the transistor's (10) gate (22) and a portion of the drain region (18, 19) that is adjacent the transistor's channel (20). The performance enhancing conductor (27) is isolated from the gate (22) by an insulator (24, 26).

Abstract translation: 使用性能增强导体（27）来减小晶体管（10）导通电阻并且还将晶体管（10）的寄生栅极减小到漏极电容（32）。 性能增强导体（27）覆盖晶体管（10）栅极（22）和与晶体管通道（20）相邻的漏极区域（18,19）的一部分。 性能增强导体（27）通过绝缘体（24,26）与栅极（22）隔离。

公开(公告)号：US5556793A

公开(公告)日：1996-09-17

申请号：US144623

申请日：1993-11-01

Applicant: Steven J. Adler ,  George W. Hawkins ,  Israel A. Lesk ,  Peter L. Pegler ,  Hassan Pirastehfar

Inventor： Steven J. Adler ,  George W. Hawkins ,  Israel A. Lesk ,  Peter L. Pegler ,  Hassan Pirastehfar

IPC: H01L21/322

CPC classification number: H01L21/3221

Abstract: A method for gettering metallic impurities from a semiconductor substrate (25). A gettering structure is fabricated in inactive areas of a semiconductor chip (31). The gettering structure is manufactured by forming an oxide (30) having a bird's head structure contacting a heavily doped region (28). The combination creates precipitation nuclei to which the metallic impurities migrate. The metallic impurities are sequestered by the precipitation nuclei or trap sites and rendered incapable of degrading the electrical characteristics of a semiconductor device.

Abstract translation: 一种用于从半导体衬底（25）吸收金属杂质的方法。 在半导体芯片（31）的无源区域中制造吸气结构。 通过形成具有与重掺杂区域（28）接触的鸟头结构的氧化物（30）来制造吸气结构。 该组合产生沉淀核，金属杂质迁移到沉淀核。 金属杂质被沉淀核或捕集点隔离，并且不能降低半导体器件的电特性。

公开(公告)号：US5434442A

公开(公告)日：1995-07-18

申请号：US884319

申请日：1992-05-11

Applicant: Israel A. Lesk ,  Hassan Pirastehfar

Inventor： Israel A. Lesk ,  Hassan Pirastehfar

IPC: G01N27/00 ,  H01L29/866

CPC classification number: G01N33/005 ,  H01L29/866

Abstract: A field plate avalanche diode has a field plate extending over the breakdown PN junction.

Abstract translation: 场板雪崩二极管具有在击穿PN结上延伸的场板。

公开(公告)号：US5371394A

公开(公告)日：1994-12-06

申请号：US153503

申请日：1993-11-15

Applicant: Gordon C. Ma ,  Hassan Pirastehfar ,  Steven J. Adler

Inventor： Gordon C. Ma ,  Hassan Pirastehfar ,  Steven J. Adler

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/68 ,  H01L21/04

CPC classification number: H01L29/66659 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/7835

Abstract: An NMOS transistor has a source and a drain composed of n+ type of semiconductor material. A substrate region composed of a p type of semiconductor material is disposed between the source and the drain. A gate region is disposed above the substrate region and between the source region and the drain region. A first implant region is disposed adjacent to the source region and the gate region. The first implant region is composed of p type of semiconductor material with a first doping concentration. A second implant region is disposed between the first implant region and the substrate. The second implant region is composed of p type of semiconductor material with a second doping concentration. The channel doping profile first and second implant regions is tailored to obtain the optimum internal electric field to maximize device transconductance, while simultaneously controlling the device threshold voltage and punch through characteristics.

Abstract translation: NMOS晶体管具有由n +型半导体材料构成的源极和漏极。 由p型半导体材料构成的衬底区域设置在源极和漏极之间。 栅极区域设置在衬底区域之上并且在源极区域和漏极区域之间。 第一注入区域邻近源极区域和栅极区域设置。 第一注入区域由具有第一掺杂浓度的p型半导体材料组成。 第二植入区域设置在第一植入区域和基底之间。 第二注入区由具有第二掺杂浓度的p型半导体材料组成。 沟道掺杂分布第一和第二注入区域被定制以获得最佳内部电场以最大化器件跨导，同时控制器件阈值电压和穿透特性。