公开(公告)号：US09836568B1

公开(公告)日：2017-12-05

申请号：US15069524

申请日：2016-03-14

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Aaron Ng ,  Ronald E. Plyler ,  Sabyasachi Das ,  Frederic Revenu

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081

Abstract: Improving timing of a circuit design may include determining, using a processor, critical feed-forward paths of the circuit design, determining, using the processor, a sequential loop having a largest loop delay within the circuit design, and iteratively cutting, using the processor, the critical feed-forward paths and feed-forward paths parallel to the cut critical feed-forward paths until a stopping condition is met. The stopping condition may be determined according to the largest loop delay. The circuit design may be modified by inserting a register at each cut feed-forward path.

公开(公告)号：US09729153B1

公开(公告)日：2017-08-08

申请号：US15234640

申请日：2016-08-11

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Benjamin S. Devlin

IPC: H03K19/096 ,  H03K19/173 ,  H03K19/177 ,  H03K19/20

CPC classification number: H03K19/1737 ,  H03K19/1776 ,  H03K19/20

Abstract: A device includes a multiplexer circuit with a plurality of input circuits. Each input circuit is connected to a respective input node and a shared output node. The input circuits are configured to pass, in response to a respective control signal, a signal between the respective input and shared output node. An output circuit is configured to store data from the shared output node in a latch mode and to act as a buffer in a pass-through mode. A control circuit is configured to switch, in response to a configuration signal, the output circuit between the latch mode and the pass-through mode.

公开(公告)号：US08988125B1

公开(公告)日：2015-03-24

申请号：US14056154

申请日：2013-10-17

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Manu Jose

IPC: H03H11/26 ,  H03K5/14

CPC classification number: H03K5/14

Abstract: A circuit for routing signals in an integrated circuit is disclosed. The circuit comprises a path having a plurality of registers coupled in series and including a source register, a destination register and at least one intermediate register; a clock generator generating a clock signal; and a delay element coupled to receive the clock signal and generate a delayed clock signal, wherein the delayed clock signal is coupled to a clock input of the at least one intermediate register. A method of routing signals in an integrated circuit is also disclosed.

Abstract translation: 公开了一种用于在集成电路中路由信号的电路。 电路包括具有串联耦合的多个寄存器的路径，包括源寄存器，目的地寄存器和至少一个中间寄存器; 产生时钟信号的时钟发生器; 以及延迟元件，其耦合以接收所述时钟信号并产生延迟的时钟信号，其中所述延迟的时钟信号耦合到所述至少一个中间寄存器的时钟输入。 还公开了一种在集成电路中路由信号的方法。

公开(公告)号：US10320386B1

公开(公告)日：2019-06-11

申请号：US15836571

申请日：2017-12-08

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Brian C. Gaide ,  Henri Fraisse

IPC: H03K19/00 ,  H03K19/003 ,  H03K19/20 ,  H03K19/0175 ,  H03K19/173 ,  H03K3/037 ,  H03K19/177

Abstract: The disclosed circuit arrangements include a logic circuit, multiple bi-stable circuits, and control circuitry coupled to the bi-stable circuits. Each bi-stable circuit has a data input, a clock input, and an output coupled to the logic circuit. The control circuitry is programmable to selectively connect outputs of the bi-stable circuits or signals at the data inputs of the plurality of bi-stable circuits to inputs of the logic circuit. The control circuitry generates one or more delayed clock signals from the clock signal, and selectively provides one of the one or more delayed clock signals or the clock signal without delay to the clock input of each of the first plurality of bi-stable circuits.

公开(公告)号：US10284185B1

公开(公告)日：2019-05-07

申请号：US15845957

申请日：2017-12-18

Applicant: Xilinx, Inc.

Inventor： Brian C. Gaide ,  Ilya K. Ganusov ,  Chi M. Nguyen ,  Robert I. Fu

IPC: H03K5/15 ,  G06F1/10 ,  G06F1/12 ,  H03K19/096 ,  H03K5/00

Abstract: The disclosed circuit arrangements include a logic circuit, input register logic coupled to the logic circuit and including a first plurality of bi-stable circuits and a control circuit coupled to the input register logic. The control circuit is configured to generate a plurality of delayed clock signals from an input clock signal. The plurality of delayed clock signals include a first delayed clock signal and a second delayed clock signal. The control circuit selectively provides one or more of the delayed clock signals or the input clock signal to clock inputs of the first plurality of bi-stable circuits and selectively provides one or more of the delayed clock signals or the input clock signal to the logic circuit. The control circuit includes a variable clock delay logic circuit configured to equalize a clock delay to the input register logic with a clock delay to the logic circuit.

公开(公告)号：US09577615B1

公开(公告)日：2017-02-21

申请号：US14792894

申请日：2015-07-07

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Benjamin S. Devlin

IPC: H03K3/017 ,  H03K3/356

CPC classification number: H03K3/356156 ,  G06F1/10 ,  H03K5/1565

Abstract: A circuit for reducing duty-cycle distortion in an integrated circuit implementing dual-edge clocking is described. The circuit also comprises a plurality of circuit elements that enable the routing of data generated at outputs of the circuit elements; a plurality of register circuits that store data at outputs of the plurality of circuit elements; a clock circuit routing a clock signal to clock inputs of the plurality of register circuits; and a pulsed-controlled register circuit coupled to an output of a circuit element and generating a pulsed output coupled to a clock input of a register of the pulse-controlled register circuit; wherein the pulsed output is coupled to the clock input of the register to enable the pulse-controlled register circuit to store data at a time that is different than an edge of the clock signal. A method of reducing duty-cycle distortion in an integrated circuit implementing dual-edge clocking is also described.

Abstract translation: 描述了实现双边沿时钟的集成电路中减小占空比失真的电路。 电路还包括多个电路元件，其能够路由在电路元件的输出处产生的数据; 多个寄存器电路，用于在多个电路元件的输出端存储数据; 将时钟信号路由到多个寄存器电路的时钟输入的时钟电路; 以及脉冲控制寄存器电路，其耦合到电路元件的输出并且产生耦合到所述脉冲控制寄存器电路的寄存器的时钟输入的脉冲输出; 其中所述脉冲输出耦合到所述寄存器的时钟输入，以使所述脉冲控制寄存器电路在与所述时钟信号的边沿不同的时间存储数据。 还描述了实现双边沿时钟的集成电路中减少占空比失真的方法。

公开(公告)号：US09537491B1

公开(公告)日：2017-01-03

申请号：US14667580

申请日：2015-03-24

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Benjamin S. Devlin

IPC: H03L7/06 ,  H03L7/08

CPC classification number: H03L7/08 ,  G06F1/06 ,  G06F1/10 ,  H03K5/15006 ,  H03K5/1502 ,  H03K19/1774

Abstract: Methods and apparatus for generating multiple phase-shifted clock signals from a base clock signal using programmable delays at the leaf level in a clock distribution network are described. One example method for generating and distributing multiple phase-shifted clock signals in a programmable integrated circuit (IC) generally includes generating a base clock signal, routing the base clock signal through a clock distribution network in the programmable IC to a leaf node, and applying one or more programmable delays to the base clock signal received from the leaf node to generate the multiple phase-shifted clock signals.

Abstract translation: 描述了使用在时钟分配网络中的叶级的可编程延迟从基本时钟信号产生多个相移时钟信号的方法和装置。 用于在可编程集成电路（IC）中生成和分配多个相移时钟信号的一个示例性方法通常包括生成基本时钟信号，将基准时钟信号通过可编程IC中的时钟分配网络路由到叶节点，以及应用 从叶节点接收的基本时钟信号的一个或多个可编程延迟以产生多个相移时钟信号。

公开(公告)号：US09372953B1

公开(公告)日：2016-06-21

申请号：US14494978

申请日：2014-09-24

Applicant: Xilinx, Inc.

Inventor： Shant Chandrakar ,  Ilya K. Ganusov

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5031 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/84

Abstract: Processing a circuit design includes determining that an operating frequency for a first placement and routing for the circuit design does not exceed a target operating frequency, distinguishing between loop paths and feed-forward paths in the circuit design, and, responsive to determining that the operating frequency does not exceed the target operating frequency, relaxing timing constraints of the feed-forward paths using a processor. A second placement and routing is performed on the loop paths and the feed-forward paths of the circuit design.

Abstract translation: 处理电路设计包括确定用于电路设计的第一布置和布线的工作频率不超过目标工作频率，区分电路设计中的环路径和前馈路径，并且响应于确定操作 频率不超过目标工作频率，使用处理器的前馈路径的放松时序约束。 在电路设计的环路径和前馈路径上进行第二次放置和布线。

公开(公告)号：US10049177B1

公开(公告)日：2018-08-14

申请号：US14792953

申请日：2015-07-07

Applicant: Xilinx, Inc.

Inventor： Benjamin S. Devlin ,  Ilya K. Ganusov

IPC: G06F17/50

Abstract: A circuit for reducing power consumed by routing clock signals in an integrated circuit is described. The circuit comprises a clock routing network comprising a clock row coupled to receive an input clock signal having a first clock frequency and a plurality of clock branches coupled to the clock row; and a plurality of circuit blocks coupled to the plurality of clock branches, each circuit block having a clock conversion circuit and a register; wherein the clock conversion circuit is programmable to generate clock pulses of an internal clock signal, coupled to the register, having a second frequency that is greater than the first frequency. A method of reducing power consumed by routing clock signals in an integrated circuit is also disclosed.

公开(公告)号：US09875330B2

公开(公告)日：2018-01-23

申请号：US14960176

申请日：2015-12-04

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Henri Fraisse ,  Ashish Sirasao ,  Alireza S. Kaviani

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5054

Abstract: Disclosed approaches for processing a circuit design include identifying duplicate instances of a module in a representation of the circuit design. A processor circuit performs folding operations for at least one pair of the duplicate instances of the module. One instance of the duplicates is removed from the circuit design, and a multiplexer is inserted. The multiplexer receives and selects one of the input signals to the duplicate instances and provides the selected input signal to the remaining instance. For each flip-flop in the remaining instance, a pipelined flip-flop is inserted. Connections to a first clock signal in the remaining instance are replaced with connections to a second clock signal having twice the frequency of the first clock signal. An alignment circuit is inserted to receive the output signal from the first instance and provide concurrent first and second output signals.