公开(公告)号：US09875330B2

公开(公告)日：2018-01-23

申请号：US14960176

申请日：2015-12-04

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Henri Fraisse ,  Ashish Sirasao ,  Alireza S. Kaviani

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5054

Abstract: Disclosed approaches for processing a circuit design include identifying duplicate instances of a module in a representation of the circuit design. A processor circuit performs folding operations for at least one pair of the duplicate instances of the module. One instance of the duplicates is removed from the circuit design, and a multiplexer is inserted. The multiplexer receives and selects one of the input signals to the duplicate instances and provides the selected input signal to the remaining instance. For each flip-flop in the remaining instance, a pipelined flip-flop is inserted. Connections to a first clock signal in the remaining instance are replaced with connections to a second clock signal having twice the frequency of the first clock signal. An alignment circuit is inserted to receive the output signal from the first instance and provide concurrent first and second output signals.

公开(公告)号：US20170207998A1

公开(公告)日：2017-07-20

申请号：US14995839

申请日：2016-01-14

Applicant: Xilinx, Inc.

Inventor： Henri Fraisse

IPC: H04L12/707 ,  H04L12/761 ,  H04L12/933

CPC classification number: H04L45/24 ,  H04L45/16 ,  H04L49/101 ,  H04L49/15 ,  H04L49/253

Abstract: Methods and systems are disclosed for selecting channels for routing signals in a multi-channel switching network. In an example implementation, pairs of the signals that can be routed together over one channel in the multi-channel switching network are determined. A model graph is generated that has a respective vertex for each of the signals. The model graph also includes respective edges for the determined pairs connecting vertices corresponding to signals of the pair. A subset of the edges that includes a maximum number of disjoint edges is determined. Pairs of signals represented by the respective vertices connected by the edge are routed over a respective one of the channels. For vertices not connected to an edge in the subset, the signals represented by the vertices are routed via a respective one of the channels.

公开(公告)号：US09235671B1

公开(公告)日：2016-01-12

申请号：US14460309

申请日：2014-08-14

Applicant: Xilinx, Inc.

Inventor： Henri Fraisse

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5054 ,  G06F2217/06

Abstract: In an example implementation, a method of implementing a circuit design for an integrated circuit (IC), includes: on at least one programmed processor, performing operations including: processing a description of the circuit design having logic elements into a graph having nodes representing the logic elements and edges representing potential pairs of the logic elements; determining a packing of pairs of the nodes to divide the graph into selected nodes and unselected nodes and selected edges and unselected edges by performing iterations of: identifying an augmenting path in the graph between a pair of unselected nodes; and modifying the selected nodes and unselected nodes and the selected edges and unselected edges based on the augmenting path; and grouping the logic elements in the description into pairs of logic elements based on the packing of pairs of the nodes.

Abstract translation: 在一个示例实现中，实现集成电路（IC）的电路设计的方法包括：在至少一个编程的处理器上，执行操作，包括：将具有逻辑元件的电路设计的描述处理成具有代表 逻辑元件和表示逻辑元件的潜在对的边; 通过执行以下迭代来确定所述节点对的打包以将所述图划分为所选择的节点和未选择的节点以及所选择的边和未选择的边：识别一对未选择的节点之间的图中的增强路径; 以及基于所述增加路径修改所选择的节点和未选择的节点以及所选择的边缘和未选择的边缘; 并且基于所述节点对的打包，将所述描述中的逻辑元素分组成逻辑元素对。

公开(公告)号：US12079484B2

公开(公告)日：2024-09-03

申请号：US18230117

申请日：2023-08-03

Applicant: XILINX, INC.

Inventor： Abhishek Kumar Jain ,  Henri Fraisse ,  Dinesh D. Gaitonde

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

Abstract: A method includes receiving a value and an identifier from a first memory and hashing the identifier to produce a memory block identifier. The method also includes routing, based on the memory block identifier, a read request to a memory block of a plurality of memory blocks and updating the value received from the first memory based on a property received from the memory block in response to the read request. The memory further includes storing the updated value in the first memory.

公开(公告)号：US10747929B1

公开(公告)日：2020-08-18

申请号：US16255496

申请日：2019-01-23

Applicant: Xilinx, Inc.

Inventor： Henri Fraisse ,  Dinesh D. Gaitonde ,  Chirag Ravishankar

IPC: G06F30/30 ,  G06F30/36 ,  G06F30/398 ,  G06F119/12

Abstract: A circuit design tool places a circuit design, and after placing detects a hold violation of a path between a first flip-flop on a first IC die and a second flip-flop on a second IC die. The circuit design tool selects a window size based on an amount of the hold violation and determines an alternative path having a delay that resolves the hold violation. The alternative path is restricted to resources within an area of the window size on the second IC die. The circuit design tool replicates a plurality of instances of the alternative path in a plurality of areas of the second IC die and then routes the circuit design using the plurality of instances of the alternative path.

公开(公告)号：US10726181B1

公开(公告)日：2020-07-28

申请号：US16502137

申请日：2019-07-03

Applicant: XILINX, INC.

Inventor： Martin L. Voogel ,  Trevor J. Bauer ,  Henri Fraisse

IPC: G06F30/394 ,  G06F30/331 ,  G06F30/392

Abstract: A programmable logic device with fabric regularity is disclosed. For example, the programmable logic device may include a plurality of similar heterogeneous logic blocks. A user's design may be implemented within a first group of heterogeneous logic blocks. The user's design may be moved or copied to a second group of heterogeneous logic blocks. More specifically, routing, timing, and/or placement information associated with the implementation of the users design in the first group of heterogeneous logic blocks may be used to implement the user's design in the second group of heterogeneous logic blocks.

公开(公告)号：US10320386B1

公开(公告)日：2019-06-11

申请号：US15836571

申请日：2017-12-08

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Brian C. Gaide ,  Henri Fraisse

IPC: H03K19/00 ,  H03K19/003 ,  H03K19/20 ,  H03K19/0175 ,  H03K19/173 ,  H03K3/037 ,  H03K19/177

Abstract: The disclosed circuit arrangements include a logic circuit, multiple bi-stable circuits, and control circuitry coupled to the bi-stable circuits. Each bi-stable circuit has a data input, a clock input, and an output coupled to the logic circuit. The control circuitry is programmable to selectively connect outputs of the bi-stable circuits or signals at the data inputs of the plurality of bi-stable circuits to inputs of the logic circuit. The control circuitry generates one or more delayed clock signals from the clock signal, and selectively provides one of the one or more delayed clock signals or the clock signal without delay to the clock input of each of the first plurality of bi-stable circuits.

公开(公告)号：US11720255B1

公开(公告)日：2023-08-08

申请号：US17184458

申请日：2021-02-24

Applicant: XILINX, INC.

Inventor： Abhishek Kumar Jain ,  Henri Fraisse ,  Dinesh D. Gaitonde

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

Abstract: A method includes receiving a value and an identifier from a first memory and hashing the identifier to produce a memory block identifier. The method also includes routing, based on the memory block identifier, a read request to a memory block of a plurality of memory blocks and updating the value received from the first memory based on a property received from the memory block in response to the read request. The memory further includes storing the updated value in the first memory.

公开(公告)号：US10445456B1

公开(公告)日：2019-10-15

申请号：US15623302

申请日：2017-06-14

Applicant: Xilinx, Inc.

Inventor： Henri Fraisse

IPC: G06F17/50

Abstract: Routing a circuit design for implementation within an integrated circuit can include determining a set of candidate paths from available paths of the integrated circuit for connecting source-sink pairs of the circuit design, wherein the set of candidate paths is initially a subset of the available paths, and generating, using a processor, an expression having a plurality of variables expressed as a conjunction of routing constraints representing legal routes of the source-sink pairs using only the candidate paths. A routing result for the circuit design can be determined by initiating execution of a SAT solver on the expression using the processor.

公开(公告)号：US20190181863A1

公开(公告)日：2019-06-13

申请号：US15836571

申请日：2017-12-08

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Brian C. Gaide ,  Henri Fraisse

IPC: H03K19/003 ,  H03K19/20 ,  H03K19/177 ,  H03K19/173 ,  H03K3/037 ,  H03K19/0175

Abstract: The disclosed circuit arrangements include a logic circuit, multiple bi-stable circuits, and control circuitry coupled to the bi-stable circuits. Each bi-stable circuit has a data input, a clock input, and an output coupled to the logic circuit. The control circuitry is programmable to selectively connect outputs of the bi-stable circuits or signals at the data inputs of the plurality of bi-stable circuits to inputs of the logic circuit. The control circuitry generates one or more delayed clock signals from the clock signal, and selectively provides one of the one or more delayed clock signals or the clock signal without delay to the clock input of each of the first plurality of bi-stable circuits.