公开(公告)号：US09836568B1

公开(公告)日：2017-12-05

申请号：US15069524

申请日：2016-03-14

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Aaron Ng ,  Ronald E. Plyler ,  Sabyasachi Das ,  Frederic Revenu

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081

Abstract: Improving timing of a circuit design may include determining, using a processor, critical feed-forward paths of the circuit design, determining, using the processor, a sequential loop having a largest loop delay within the circuit design, and iteratively cutting, using the processor, the critical feed-forward paths and feed-forward paths parallel to the cut critical feed-forward paths until a stopping condition is met. The stopping condition may be determined according to the largest loop delay. The circuit design may be modified by inserting a register at each cut feed-forward path.