公开(公告)号：US20060091554A1

公开(公告)日：2006-05-04

申请号：US11311546

申请日：2005-12-19

申请人： Wei Pan ,  Yoshi Ono ,  David Evans ,  Sheng Hsu

发明人： Wei Pan ,  Yoshi Ono ,  David Evans ,  Sheng Hsu

IPC分类号： H01L23/48

CPC分类号： H01L21/28562 ,  H01L21/76841 ,  H01L2221/1078

摘要： A multi-layered barrier metal thin film is deposited on a substrate by atomic layer chemical vapor deposition (ALCVD). The multi-layer film may comprise several different layers of a single chemical species, or several layers each of distinct or alternating chemical species. In a preferred embodiment, the multi-layer barrier thin film comprises a Tantalum Nitride layer on a substrate, with a Titanium Nitride layer deposited thereon. The thickness of the entire multi-layer film may be approximately fifty Angstroms. The film has superior film characteristics, such as anti-diffusion capability, low resistivity, high density, and step coverage, when compared to films deposited by conventional chemical vapor deposition (CVD). The multi-layered barrier metal thin film of the present invention has improved adhesion characteristics and is particularly suited for metallization of a Copper film thereon.

摘要翻译： 通过原子层化学气相沉积（ALCVD）将多层阻挡金属薄膜沉积在衬底上。 多层膜可以包括单个化学物质的几个不同层，或者各个不同的或交替的化学物质的几个层。 在优选实施例中，多层阻挡薄膜包括在衬底上的氮化钽层，其上沉积有氮化钛层。 整个多层膜的厚度可以是大约50埃。 当与通过常规化学气相沉积（CVD）沉积的膜相比时，该膜具有优异的膜特性，例如抗扩散能力，低电阻率，高密度和台阶覆盖。 本发明的多层阻挡金属薄膜具有改善的粘合特性，特别适用于其上的铜膜的金属化。

公开(公告)号：US20070004226A1

公开(公告)日：2007-01-04

申请号：US11174350

申请日：2005-07-01

申请人： Douglas Tweet ,  Yoshi Ono ,  David Evans ,  Sheng Hsu

发明人： Douglas Tweet ,  Yoshi Ono ,  David Evans ,  Sheng Hsu

IPC分类号： H01L21/31

CPC分类号： H01L21/02192 ,  H01L21/02197 ,  H01L21/0228 ,  H01L21/3147

摘要： A method of controlling strain in a single-crystal, epitaxial oxide film, includes preparing a silicon substrate; forming a silicon alloy layer taken from the group of silicon alloy layer consisting of Si1-xGex and Si1-yCy on the silicon substrate; adjusting the lattice constant of the silicon alloy layer by selecting the alloy material content to adjust and to select a type of strain for the silicon alloy layer; depositing a single-crystal, epitaxial oxide film, by atomic layer deposition, taken from the group of oxide films consisting of perovskite manganite materials, single crystal rare-earth oxides and perovskite oxides, not containing manganese; and rare earth binary and ternary oxides, on the silicon alloy layer; and completing a desired device.

摘要翻译： 一种控制单晶外延氧化膜中的应变的方法包括制备硅衬底; 从由Si 1-x Ge x Si和Si 1-y C C组成的硅合金层组形成硅合金层 > y ; 通过选择合金材料含量来调整硅合金层的晶格常数，并选择一种用于硅合金层的应变; 从由不含锰的钙钛矿亚锰酸盐材料，单晶稀土氧化物和钙钛矿氧化物组成的氧化膜组中，通过原子层沉积法沉积单晶外延氧化膜; 和稀土二元和三元氧化物，在硅合金层上; 并完成所需的设备。

公开(公告)号：US20050266686A1

公开(公告)日：2005-12-01

申请号：US10855088

申请日：2004-05-27

申请人： Wei-Wei Zhuang ,  Tingkai Li ,  Wei Pan ,  David Evans ,  Sheng Hsu

发明人： Wei-Wei Zhuang ,  Tingkai Li ,  Wei Pan ,  David Evans ,  Sheng Hsu

IPC分类号： C23C18/12 ,  C30B23/02 ,  C30B29/24 ,  H01L21/44 ,  H01L45/00

CPC分类号： C23C18/1216 ,  C23C18/1225 ,  C23C18/1241 ,  C23C18/1283 ,  C30B23/02 ,  C30B29/24 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147 ,  H01L45/1608

摘要： A method of fabricating a CMR thin film for use in a semiconductor device includes preparing a CMR precursor in the form of a metal acetate based acetic acid solution; preparing a wafer; placing a wafer in a spin-coating chamber; spin-coating and heating the wafer according to the following: injecting the CMR precursor into a spin-coating chamber and onto the surface of the wafer in the spin-coating chamber; accelerating the wafer to a spin speed of between about 1500 RPM to 3000 RPM for about 30 seconds; baking the wafer at a temperature of about 180° C. for about one minute; ramping the temperature to about 230° C.; baking the wafer for about one minute at the ramped temperature; annealing the wafer at about 500° C. for about five minutes; repeating said spin-coating and heating steps at least three times; post-annealing the wafer at between about 500° C. to 600° C. for between about one to six hours in dry, clean air; and completing the semiconductor device.

摘要翻译： 制造用于半导体器件的CMR薄膜的方法包括制备基于金属乙酸酯的乙酸溶液形式的CMR前体; 准备晶圆; 将晶片放置在旋涂室中; 根据以下步骤旋涂和加热晶片：将CMR前体注入旋涂室并在旋涂室中的晶片表面上; 将晶片加速至约1500RPM至3000RPM之间的旋转速度约30秒; 在约180℃的温度下烘烤晶片约1分钟; 将温度升高至约230℃; 在升温下烘烤晶片约1分钟; 在约500℃退火晶片约5分钟; 重复所述旋涂和加热步骤至少三次; 在约500℃至600℃之间将晶片退火约1至6小时，在干燥，干净的空气中进行退火; 并完成半导体器件。

公开(公告)号：US20050003663A1

公开(公告)日：2005-01-06

申请号：US10903610

申请日：2004-07-29

申请人： Wei Pan ,  Jer-Shen Maa ,  David Evans ,  Sheng Hsu

发明人： Wei Pan ,  Jer-Shen Maa ,  David Evans ,  Sheng Hsu

IPC分类号： H01L21/3205 ,  C23C16/02 ,  C23C16/18 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76843 ,  C23C16/0209 ,  C23C16/18 ,  H01L21/28556 ,  H01L21/76864 ,  H01L21/76876

摘要： A rapid thermal process (RTP) provides steps wherein silicon wafers that are pre-coated with barrier metal films by either in-situ or ex-situ CVD or physical vapor deposition (PVD) are pre-treated, prior to deposition of a Cu film thereon, in a temperature range of between 250 and 550 degrees Celsius in a non-reactive gas such as hHydrogen gas (H2), argon (Ar), or helium (He), or in an ambient vacuum. The chamber pressure typically is between 0.1 mTorr and 20 Torr, and the RTP time typically is between 30 to 100 seconds. Performing this rapid thermal process before deposition of the Cu film results in a thin, shiny, densely nucleated, and adhesive Cu film deposited on a variety of barrier metal surfaces. The pre-treatment process eliminates variations in the deposited Cu film caused by Cu precursors and is insensitive to variation in precursor composition, volatility, and other precursor variables. Accordingly, the process disclosed herein is an enabling technology for the use of metal organic CVD (MOCVD) Cu in IC fabrication.

摘要翻译： 快速热处理（RTP）提供了在沉积Cu膜之前预处理通过原位或原位CVD或物理气相沉积（PVD）预涂覆有阻挡金属膜的硅晶片的步骤 在非反应性气体例如氢气（H 2），氩气（Ar）或氦气（He）中，或在环境真空中，在250-550℃的温度范围内。 室压力通常在0.1mTorr和20Torr之间，并且RTP时间通常在30至100秒之间。 在沉积Cu膜之前进行这种快速热处理会导致沉积在各种阻挡金属表面上的薄而有光泽，致密成核和粘附的Cu膜。 预处理过程消除了由Cu前体引起的沉积的Cu膜的变化，并且对前体组成，挥发性和其它前体变量的变化不敏感。 因此，本文公开的方法是在IC制造中使用金属有机CVD（MOCVD）Cu的使能技术。

公开(公告)号：US20050207265A1

公开(公告)日：2005-09-22

申请号：US11130983

申请日：2005-05-16

申请人： Sheng Hsu ,  Tingkai Li ,  David Evans ,  Wei-Wei Zhuang ,  Wei Pan

发明人： Sheng Hsu ,  Tingkai Li ,  David Evans ,  Wei-Wei Zhuang ,  Wei Pan

IPC分类号： H01L27/10 ,  G11C11/15 ,  G11C13/00 ,  H01L45/00 ,  G11C8/02

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1625

摘要： Asymmetrically structured memory cells and a fabrication method are provided. The method comprises: forming a bottom electrode; forming an electrical pulse various resistance (EPVR) first layer having a polycrystalline structure over the bottom electrode; forming an EPVR second layer adjacent the first layer, with a nano-crystalline or amorphous structure; and, forming a top electrode overlying the first and second EPVR layers. EPVR materials include CMR, high temperature super conductor (HTSC), or perovskite metal oxide materials. In one aspect, the EPVR first layer is deposited with a metalorganic spin coat (MOD) process at a temperature in the range between 550 and 700 degrees C. The EPVR second layer is formed at a temperature less than, or equal to the deposition temperature of the first layer. After a step of removing solvents, the MOD deposited EPVR second layer is formed at a temperature less than, or equal to the 550 degrees C.

摘要翻译： 提供了非对称结构的存储单元和制造方法。 该方法包括：形成底部电极; 在底部电极上形成具有多晶结构的电脉冲各种电阻（EPVR）第一层; 用纳米结晶或无定形结构形成邻近第一层的EPVR第二层; 并且形成覆盖在第一和第二EPVR层上的顶部电极。 EPVR材料包括CMR，高温超导体（HTSC）或钙钛矿金属氧化物材料。 在一个方面，EPVR第一层在550-700℃的温度范围内用金属有机旋涂（MOD）工艺沉积.EPVR第二层是在小于或等于沉积温度 的第一层。 在除去溶剂的步骤之后，将MOD沉积的EPVR第二层在小于或等于550℃的温度下形成。

公开(公告)号：US20050037520A1

公开(公告)日：2005-02-17

申请号：US10640770

申请日：2003-08-13

申请人： Wei-Wei Zhuang ,  Tingkai Li ,  David Evans ,  Sheng Hsu ,  Wei Pan

发明人： Wei-Wei Zhuang ,  Tingkai Li ,  David Evans ,  Sheng Hsu ,  Wei Pan

IPC分类号： H01L27/04 ,  H01L21/20 ,  H01L21/822 ,  H01L45/00 ,  H01L21/00

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608

摘要： A method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer includes depositing, by MOCVD, a seed layer of PCMO, in highly crystalline form, thin film, having a thickness of between about 50 Å to 300 Å, depositing a second PCMO thin film layer on the seed layer, by spin coating, having a thickness of between about 500 Å to 3000 Å, to form a combined PCMO layer; increasing the resistance of the combined PCMO film in a semiconductor device by applying a negative electric pulse of between about −4V to −5V, having a pulse width of between about 75 nsec to 1 μsec; and decreasing the resistance of the combined PCMO layer in a semiconductor device by applying a positive electric pulse of between about +2.5V to +4V, having a pulse width greater than 2.0 μsec.

摘要翻译： 当与高度结晶的种子层集成时，用于获得PCMO薄膜上的可逆电阻开关的方法包括通过MOCVD沉积高度结晶形式的PCMO的种子层，薄膜的厚度为约50埃至300埃 通过旋转涂覆沉积种子层上的第二PCMO薄膜层，其厚度为约500埃至3000埃以形成组合的PCMO层; 通过施加约-4V至-5V之间的脉冲宽度在约75ns至1个音箱之间的负电脉冲来增加半导体器件中组合的PCMO膜的电阻; 并且通过施加脉冲宽度大于2.0个音箱的约+ 2.5V至+ 4V之间的正电脉冲来降低半导体器件中组合的PCMO层的电阻。

公开(公告)号：US20060099724A1

公开(公告)日：2006-05-11

申请号：US11314222

申请日：2005-12-21

申请人： Sheng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei Pan ,  Wei-Wei Zhuang ,  David Evans ,  Masayuki Tajiri

发明人： Sheng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei Pan ,  Wei-Wei Zhuang ,  David Evans ,  Masayuki Tajiri

IPC分类号： H01L21/00 ,  H01L21/20

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/51 ,  G11C2213/56 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147

摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7-X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1-XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.

摘要翻译： 提供了一种用于形成缓冲层存储单元的方法。 该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。 在该方法的一些方面，半导体缓冲层由YBa 2 N 3 O 7-X（YBCO），氧化铟（In 2或2 O 3）或氧化钌（RuO 2 N 2），其厚度在10-200纳米（nm）的范围内。 顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr 1-X C x MnO 3（PCMO）存储膜，其中x在0.1之间的区域 和0.6，厚度在10至200nm的范围内。

公开(公告)号：US20050054119A1

公开(公告)日：2005-03-10

申请号：US10755654

申请日：2004-01-12

申请人： Sheng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei Pan ,  Wei-Wei Zhuang ,  David Evans ,  Masayuki Tajiri

发明人： Sheng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei Pan ,  Wei-Wei Zhuang ,  David Evans ,  Masayuki Tajiri

IPC分类号： H01L27/10 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00 ,  H01L21/00 ,  G11C11/00 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/51 ,  G11C2213/56 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147

摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7−X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1−XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.

摘要翻译： 提供了一种用于形成缓冲层存储单元的方法。 该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。 在该方法的某些方面，半导体缓冲层由厚度在10至200纳米（nm）范围内的YBa2Cu3O7-X（YBCO），氧化铟（In2O3）或氧化钌（RuO2）形成。 顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr1-XCaXMnO3（PCMO）记忆膜，其中x在0.1和0.6之间的区域中，厚度在10至200nm的范围内。

公开(公告)号：US20050014296A1

公开(公告)日：2005-01-20

申请号：US10621863

申请日：2003-07-16

申请人： Tingkai Li ,  Wei Pan ,  Robert Barrowcliff ,  David Evans ,  Sheng Hsu

发明人： Tingkai Li ,  Wei Pan ,  Robert Barrowcliff ,  David Evans ,  Sheng Hsu

IPC分类号： H01L21/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115

CPC分类号： H01L27/11502 ,  H01L21/28291 ,  H01L21/31604 ,  H01L27/11585 ,  H01L27/1159 ,  H01L28/57 ,  H01L29/6684

摘要： A method of forming an H2 passivation layer in an FeRAM includes preparing a silicon substrate; depositing a layer of TiOx thin film, where 0

摘要翻译： 在FeRAM中形成H 2钝化层的方法包括制备硅衬底; 在大马士革结构上沉积一层TiOx薄膜，其中0

公开(公告)号：US20060180816A1

公开(公告)日：2006-08-17

申请号：US11058505

申请日：2005-02-14

申请人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Hsu

发明人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Hsu

IPC分类号： H01L29/26

CPC分类号： H05B33/145

摘要： A method is provided for forming a Si electroluminescence (EL) device for emitting light at short wavelengths. The method comprises: providing a substrate; forming a first insulator layer overlying the substrate; forming a silicon-rich silicon oxide (SRSO) layer overlying the first insulator layer, embedded with nanocrystalline Si having a size in the range of 0.5 to 5 nm; forming a second insulator layer overlying the SRSO layer; and, forming a top electrode. Typically, the SRSO has a Si richness in the range of 5 to 40%. In one aspect, the SRSO layer is formed using a DC sputtering process. In another aspect, the SRSO formation step includes a rapid thermal annealing (RTA) process subsequent to depositing the SRSO. Likewise, thermal oxidation or plasma oxidation can be performed subsequent to the SRSO layer deposition. The size of Si nanocrystals is decreased in response to above-mentioned deposition, annealing, and oxidation processes.

摘要翻译： 提供一种用于形成用于发射短波长的光的Si电致发光（EL）装置的方法。 该方法包括：提供衬底; 形成覆盖所述衬底的第一绝缘体层; 形成覆盖在第一绝缘体层上的富硅氧化物（SRSO）层，其中嵌入尺寸在0.5至5nm范围内的纳米晶体Si; 形成覆盖所述SRSO层的第二绝缘体层; 并形成顶部电极。 通常，SRSO的Si浓度范围为5〜40％。 在一个方面，使用DC溅射工艺形成SRSO层。 另一方面，SRSO形成步骤包括在沉积SRSO之后的快速热退火（RTA）工艺。 同样地，可以在SRSO层沉积之后进行热氧化或等离子体氧化。 响应于上述沉积，退火和氧化过程，Si纳米晶体的尺寸减小。