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公开(公告)号：US10482969B2
公开(公告)日：2019-11-19
申请号：US15874839
申请日：2018-01-18
Applicant: Western Digital Technologies, Inc.
Inventor： Refael Ben-Rubi
Abstract: Apparatuses, systems, methods, and computer program products are disclosed for distributed program operation. One apparatus includes a non-volatile storage controller that identifies a threshold number of bit flips that can be corrected in an amount of read data and a memory die comprising a plurality of non-volatile memory cells. Here, the memory die receives the threshold number of bit flips from the non-volatile storage controller, programs data to a set of the non-volatile memory cells over a first number of program loop cycles, and programs the data to the set of non-volatile memory cells over an additional number of program loop cycles in response to the amount of bit flips in the set of memory cells exceeding the threshold number of bit flips.
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公开(公告)号：US10923178B1
公开(公告)日：2021-02-16
申请号：US16802638
申请日：2020-02-27
Applicant: Western Digital Technologies, Inc.
Inventor： Refael Ben-Rubi
IPC: G06F11/00 , G11C11/408 , G11C11/4093 , G06F13/16 , G11C11/56 , G11C8/12
Abstract: The present disclosure generally relates to enhanced write performance by taking into consideration user write performance preferences as well as enhanced post write read (EPWR) scheduling. The user provides the write performance preferences to the data storage device. When a write operation happens, the data storage device checks the write performance preference for the current LBA as well as the write performance preference for the previous LBA. The data storage device will also check whether the current word line is scheduled for EPWR. Based upon the write performance preferences for the LBAs and the EPWR scheduling, the data can be written out of order to meet the user's write performance preferences. If the data is written out of order, the flash translation layer (FLT) is informed of the switch.
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公开(公告)号：US12165735B2
公开(公告)日：2024-12-10
申请号：US17956784
申请日：2022-09-29
Applicant: Western Digital Technologies, Inc.
Inventor： Refael Ben-Rubi
Abstract: The present disclosure generally relates to optimizing memory storage performance and power usage. Read operations from flash memory are comprised of a sense operation and a read transfer operation. Usually, these two operations are performed in parallel to achieve high read performance. However, these two operations typically do not take the same amount of time, leading to inefficiencies. By measuring sense busy time, the read transfer clock may be set accordingly so the two operations are equal in time. In so doing, the system will be optimized from both a performance and power consumption point of view.
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公开(公告)号：US11531499B2
公开(公告)日：2022-12-20
申请号：US17192142
申请日：2021-03-04
Applicant: Western Digital Technologies, Inc.
Inventor： Refael Ben-Rubi
IPC: G06F3/06
Abstract: A data storage device includes a memory device and a controller coupled to the memory device. When a program operation occurs, the controller is configured to determine a decode time for the data prior to programming the data to the memory device. The decode time determined by decoding the encoded data. A number of program loop cycles is determined using the decode time. The data is programmed to the memory device with the number of program loop cycles determined.
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公开(公告)号：US11630785B2
公开(公告)日：2023-04-18
申请号：US17184529
申请日：2021-02-24
Applicant: Western Digital Technologies, Inc.
Inventor： Refael Ben-Rubi , Moshe Cohen
Abstract: The present disclosure generally relates to improving data transfer speed. A data storage device includes both a controller and a memory device. The controller provides instructions regarding read and/or write commands to the memory device through the use of control lines. The data to be written/read is transferred between the controller and the memory device along data lines. The control lines typically are not used during data transfer. During data transfer, the control lines can be used to increase data transfer speed by utilizing the otherwise idle control lines for data transfer in addition to the data lines. Hence, data transfer speed is increased by using not only the data lines, but additionally the control lines. Once the data transfer is complete, the control lines return to their legacy function.
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Patent Agency Ranking
公开(公告)号：US10579611B2
公开(公告)日：2020-03-03
申请号：US15614044
申请日：2017-06-05
Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
Inventor： Refael Ben-Rubi , Moshe Cohen , Ahiad Turgeman , Uri Shir , David Chaim Brief
Abstract: An apparatus includes one or more processors configured to execute instructions to generate a plurality of event results that includes a first event result and a second event result. The apparatus further includes a first buffer coupled to the one or more processors and a second buffer coupled to the first buffer. The first buffer is configured to store the plurality of event results. The apparatus further includes a circuit coupled to the first buffer. The first buffer is further configured to provide the first event result to the second buffer in response to detection by the circuit of a failure condition associated with the first event result.
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公开(公告)号：US20200004628A1
公开(公告)日：2020-01-02
申请号：US16021857
申请日：2018-06-28
Applicant: Western Digital Technologies, Inc.
Inventor： Refael Ben-Rubi , Eran Sharon
IPC: G06F11/10 , G06F12/0866 , H03M13/11 , G06F3/06
Abstract: Enhanced error correction for data stored in storage devices are presented herein. A storage controller retrieves an initial encoded data segment stored on a storage media, computes information relating to errors resultant from decoding the initial encoded data segment, and stores the information in a cache. The storage controller retrieves subsequent encoded data segments stored on the storage media, augments a decoder using at least the information retrieved from the cache, and decodes the subsequent encoded data with the decoder to produce resultant data.
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公开(公告)号：US10461804B2
公开(公告)日：2019-10-29
申请号：US15879680
申请日：2018-01-25
Applicant: Western Digital Technologies, Inc.
Inventor： Moshe Cohen , Refael Ben-Rubi
Abstract: A method for elimination of crosstalk effects in a non-volatile storage is disclosed, having steps of identifying at least one line connected to the non-volatile storage that causes crosstalk effects to another line connected to the non-volatile storage, sending a command to the non-volatile storage to replace the at least one line causing crosstalk effects, selecting at least one line to replace the at least one line causing crosstalk effects with a spare line and replacing the at least one line causing crosstalk effects with the spare line.
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公开(公告)号：US12164775B2
公开(公告)日：2024-12-10
申请号：US17958594
申请日：2022-10-03
Applicant: Western Digital Technologies, Inc.
Inventor： Refael Ben-Rubi
Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command to read data from the memory device or a write command to write data to the memory device from a host device, determine whether a bottleneck exists in a data/control path between the host device and the memory device, wherein the bottleneck exists in a hardware module of the plurality of hardware modules, and execute a bottleneck release operation when the bottleneck exists in the data/control path between the host device and the memory device, wherein the bottleneck release operation is dependent on whether the bottleneck exists in the input queue. The bottleneck release operation includes changing a clock of the hardware module, moving the command to a different hardware module configured to process the command, and combinations thereof.
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公开(公告)号：US12105574B2
公开(公告)日：2024-10-01
申请号：US17729854
申请日：2022-04-26
Applicant: Western Digital Technologies, Inc.
Inventor： Refael Ben-Rubi
IPC: G06F1/3234 , G06F1/08 , G06F1/3203 , G06F1/3221 , G06F1/3225 , G06F1/324 , G06F3/06 , G06F9/54 , G06F11/34
CPC classification number: G06F1/3268 , G06F1/324 , G06F1/08 , G06F1/3203 , G06F1/3221 , G06F1/3225 , G06F1/3275 , G06F3/0625 , G06F3/0656 , G06F9/546 , G06F11/3409
Abstract: The present disclosure generally relates to ensuring a data storage device consumes as little power as possible. Different HW modules in the data storage device can operate at different frequencies to ensure any bottleneck HW modules operate at as fast a frequency as possible, while non-bottleneck HW modules operate at slower frequencies and hence, consume less power. The frequency for each HW modules is dynamic and is adjusted based upon detected bottlenecks so that the data storage device can operate as efficiently as possible and consume as little power as possible.
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