公开(公告)号：US20230317779A1

公开(公告)日：2023-10-05

申请号：US18206618

申请日：2023-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Heng Liu ,  Chia-Wei Huang ,  Hsin-Jen Yu ,  Yung-Feng Cheng ,  Ming-Jui Chen

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L29/66795 ,  H01L21/76224 ,  H01L29/7851

Abstract: A method for fabricating minimal fin length includes the steps of first forming a fin-shaped structure extending along a first direction on a substrate, forming a first single-diffusion break (SDB) trench and a second SDB trench extending along a second direction to divide the fin-shaped structure into a first portion, a second portion, and a third portion, and then performing a fin-cut process to remove the first portion and the third portion.

公开(公告)号：US20190013394A1

公开(公告)日：2019-01-10

申请号：US16121567

申请日：2018-09-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tan-Ya Yin ,  Chia-Wei Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a patterned metal gate layer. The substrate includes a first fin segment and a second fin segment respectively protruding from a top surface of the substrate. The first fin segment and the second fin segment respectively extend along a first direction and are arranged along a second direction, the first fin segment comprises a first fin structure at an end of the first segment, and the second fin segment comprises a first recess at an end of the second fin segment, and the first recess and the first fin structure are arranged along the second direction. The patterned metal gate layer is disposed on the substrate, and the patterned metal gate layer covers the first fin structure.

公开(公告)号：US10139723B2

公开(公告)日：2018-11-27

申请号：US15361007

申请日：2016-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-I Wei ,  Chia-Wei Huang ,  Yung-Feng Cheng

IPC: G06F17/50 ,  G03F1/36 ,  G03F1/84

Abstract: A method of forming a photomask is provided. A first layout pattern is first provided to a computer system and followed by generating an assist feature pattern by the computer system based on the first layout pattern and adding the assist feature pattern into the first layout pattern to form a second layout pattern. Thereafter, an optical proximity correction process is performed with reference to both the first layout pattern and the assist feature pattern to the second layout pattern without altering the assist feature pattern to form a third layout pattern by the computer system. Then, the third layout pattern is output to form a photomask.

公开(公告)号：US09786647B1

公开(公告)日：2017-10-10

申请号：US15092630

申请日：2016-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yung-Feng Cheng ,  Yu-Tse Kuo ,  Chia-Wei Huang ,  Li-Ping Huang ,  Shu-Ru Wang

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/11 ,  H01L27/02

CPC classification number: H01L27/0207 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1104

Abstract: A semiconductor layout structure includes a substrate comprising a cell edge region and a dummy region abutting thereto, a plurality of dummy contact patterns disposed in the dummy region and arranged along a first direction, and a plurality of dummy gate patterns disposed in the dummy region and arranged along the first direction. The dummy contact patterns and the dummy gate patterns are alternately arranged. Each dummy contact pattern includes an inner dummy contact proximal to the cell edge region and an outer dummy contact distal to the cell edge region, and the inner dummy contact and the outer dummy contact are arranged along a second direction perpendicular to the first direction and spaced apart from each other by a first gap.

公开(公告)号：US09524361B2

公开(公告)日：2016-12-20

申请号：US14690491

申请日：2015-04-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ting-Cheng Tseng ,  Ming-Jui Chen ,  Chia-Wei Huang

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5081

Abstract: A method for decomposing a layout of an integrated circuit is provided. First, a layout of the integrated circuit is imported, wherein the layout comprises a plurality of sub patterns in a cell region, and a first direction and a second direction are defined thereon. Next, one sub pattern positioned at a corner of the cell region is assigned to an anchor pattern. Then, the sub patterns in the row same as the anchor pattern along the second direction is assigned to the first group. Finally, the rest of the sub patterns are decomposed into the first group and the second group according to a design rule, wherein the sub patterns in the same line are decomposed into the first group and the second group alternatively.

Abstract translation: 提供一种用于分解集成电路的布局的方法。 首先，导入集成电路的布局，其中布局包括单元区域中的多个子图案，并且在其上限定第一方向和第二方向。 接下来，将位于单元格区域的角落的一个子图案分配给锚图案。 然后，将与沿着第二方向的锚定图案相同的行中的子图案分配给第一组。 最后，根据设计规则，剩余的子图案被分解为第一组和第二组，其中同一行中的子图案被分解成第一组和第二组。

公开(公告)号：US09316901B2

公开(公告)日：2016-04-19

申请号：US14259173

申请日：2014-04-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Chia-Wei Huang ,  Chun-Hsien Huang ,  Shih-Chun Tsai ,  Kai-Lin Chuang

IPC: G03F9/00 ,  G03F1/36 ,  G03F1/70 ,  G03F1/68

CPC classification number: G03F1/36 ,  G03F1/00 ,  G03F1/68 ,  G03F1/70

Abstract: A method for forming patterns includes the following steps. A first layout including a first target pattern and a first unprintable dummy pattern is provided. A second layout including a second target pattern and a second printable dummy pattern are provided, wherein at least part of the second printable dummy pattern overlaps the first unprintable dummy pattern exposure limit, such that the second printable dummy pattern cannot be formed in a wafer.

Abstract translation: 形成图案的方法包括以下步骤。 提供了包括第一目标图案和第一不可打印虚设图案的第一布局。 提供包括第二目标图案和第二可打印虚拟图案的第二布局，其中第二可打印虚拟图案的至少一部分与第一不可打印虚设图案曝光极限重叠，使得第二可打印虚设图案不能形成在晶片中。

公开(公告)号：US09141744B2

公开(公告)日：2015-09-22

申请号：US13968391

申请日：2013-08-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Shih-Fang Hong ,  Chia-Wei Huang ,  Ming-Jui Chen ,  Shih-Fang Tzou ,  Ming-Te Wei

IPC: G06F17/50 ,  G03F1/00

CPC classification number: G06F17/5068 ,  G03F1/144 ,  G03F1/36

Abstract: A method for generating a layout pattern is provided. First, a layout pattern is provided to a computer system and is classified into two sub-patterns and a blank pattern. Each of the sub-patterns has pitches in simple integer ratios and the blank pattern is between the two sub-patterns. Then, a plurality of first stripe patterns and at least two second stripe patterns are generated. The edges of the first stripe patterns are aligned with the edges of the sub-patterns and the first stripe patterns have equal spacings and widths. The spacings or widths of the second stripe patterns are different from that of the first stripe patterns.

Abstract translation: 提供了一种用于生成布局图案的方法。 首先，将布局图案提供给计算机系统，并将其分为两个子图案和空白图案。 每个子图案具有简单整数比例的间距，并且空白图案在两个子图案之间。 然后，生成多个第一条纹图案和至少两个第二条纹图案。 第一条形图案的边缘与子图案的边缘对齐，并且第一条纹图案具有相等的间隔和宽度。 第二条纹图案的间距或宽度与第一条纹图案的间距或宽度不同。

公开(公告)号：US20140282295A1

公开(公告)日：2014-09-18

申请号：US13802833

申请日：2013-03-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Ming-Jui Chen ,  Ching-Chun Huang ,  Chia-Wei Huang ,  Yu-Feng Chao ,  Yu-Chuan Chang

IPC: G06F17/50

CPC classification number: H01L21/76816 ,  G03F1/36 ,  H01L21/76807

Abstract: The present invention provides a method for forming at least a photo mask. A first photo-mask pattern relating to a first structure is provides. A second photo-mask pattern relating to a second structure is provides. A third photo-mask pattern relating to a third structure is provides. The first structure, the second structure and the third structure are disposed in a semiconductor structure in sequence. An optical proximity process including a comparison step is provided, wherein the comparison step includes comparing the first photo-mask pattern and the third photo-mask pattern. Last, the first photo-mask pattern is import to form a first mask, the second photo-mask pattern is import to form a second mask, and the third photo-mask pattern is import to form a third mask. The present invention further provides an OPC method.

Abstract translation: 本发明提供一种至少形成光掩模的方法。 提供与第一结构相关的第一光掩模图案。 提供与第二结构相关的第二光掩模图案。 提供了与第三结构相关的第三光掩模图案。 第一结构，第二结构和第三结构依次设置在半导体结构中。 提供了包括比较步骤的光学邻近处理，其中比较步骤包括比较第一光掩模图案和第三光掩模图案。 最后，导入第一光掩模图案以形成第一掩模，第二光掩模图案被导入以形成第二掩模，并且导入第三光掩模图案以形成第三掩模。 本发明还提供一种OPC方法。

公开(公告)号：US20220157933A1

公开(公告)日：2022-05-19

申请号：US17118630

申请日：2020-12-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Heng Liu ,  Chia-Wei Huang ,  Hsin-Jen Yu ,  Yung-Feng Cheng ,  Ming-Jui Chen

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L29/66

Abstract: A method for fabricating minimal fin length includes the steps of first forming a fin-shaped structure extending along a first direction on a substrate, forming a first single-diffusion break (SDB) trench and a second SDB trench extending along a second direction to divide the fin-shaped structure into a first portion, a second portion, and a third portion, and then performing a fin-cut process to remove the first portion and the third portion.

公开(公告)号：US10446663B2

公开(公告)日：2019-10-15

申请号：US16121567

申请日：2018-09-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tan-Ya Yin ,  Chia-Wei Huang

IPC: H01L31/119 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/308 ,  H01L29/06

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a patterned metal gate layer. The substrate includes a first fin segment and a second fin segment respectively protruding from a top surface of the substrate. The first fin segment and the second fin segment respectively extend along a first direction and are arranged along a second direction, the first fin segment comprises a first fin structure at an end of the first fin segment, and the second fin segment comprises a first recess at an end of the second fin segment, and the first recess and the first fin structure are arranged along the second direction. The patterned metal gate layer is disposed on the substrate, and the patterned metal gate layer covers the first fin structure.