公开(公告)号：US12096608B2

公开(公告)日：2024-09-17

申请号：US17493251

申请日：2021-10-04

Applicant: Unisantis Electronics Singapore Pte. Ltd.

Inventor： Fujio Masuoka ,  Nozomu Harada ,  Yisuo Li

IPC: H10B10/00 ,  H10K59/121

CPC classification number: H10B10/12 ,  H10K59/121 ,  G09G2300/0819 ,  G09G2300/0823

Abstract: In a SRAM cell, a Si pillar, which is a selection SGT in upper row of Si pillars, is located on the left end in X direction. A Si pillar, which is a selection SGT in lower row of Si pillars, is located on the right end. The Si pillar of the lower row is present in a width of an area extended from a contact hole in Y direction in planar view. Then, the Si pillar of the upper row is present in a width of an area extended from a contact hole in Y direction in planar view. In each of the upper row and the lower row, a TiN layer, which is a gate electrode for a loading SGT and a driving SGT, is formed to contact at side surface of entire gate region in a vertical direction between the corresponding Si pillars.

公开(公告)号：US08609494B2

公开(公告)日：2013-12-17

申请号：US13895956

申请日：2013-05-16

Applicant: Unisantis Electronics Singapore Pte. Ltd.

Inventor： Fujio Masuoka ,  Hiroki Nakamura ,  Shintaro Arai ,  Tomohiko Kudo ,  Yu Jiang ,  King-Jien Chui ,  Yisuo Li ,  Xiang Li ,  Zhixian Chen ,  Nansheng Shen ,  Vladimir Bliznetsov ,  Kavitha Devi Buddharaju ,  Navab Singh

IPC: H01L29/78

CPC classification number: H01L29/66484 ,  H01L21/823885 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/78642

Abstract: The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.

Abstract translation: 半导体器件包括：平面硅层上的柱状硅层; 形成在柱状硅层的底部区域中的第一n +型硅层; 形成在柱状硅层的上部区域的第二n +型硅层; 栅极绝缘膜，形成在第一和第二n +型硅层之间的沟道区的周边; 栅电极，形成在所述栅极绝缘膜的周边，并具有第一金属 - 硅化合物层; 形成在栅电极和平面硅层之间的绝缘膜，形成在柱状硅层的上侧壁中的绝缘膜侧壁; 形成在所述平面硅层中的第二金属 - 硅化合物层; 以及形成在第二n +型硅层上的电接触。

公开(公告)号：US20220028869A1

公开(公告)日：2022-01-27

申请号：US17493251

申请日：2021-10-04

Applicant: Unisantis Electronics Singapore Pte. Ltd.

Inventor： Fujio MASUOKA ,  Nozomu HARADA ,  Yisuo Li

IPC: H01L27/11

Abstract: In a SRAM cell, a Si pillar, which is a selection SGT in upper row of Si pillars, is located on the left end in X direction. A Si pillar, which is a selection SGT in lower row of Si pillars, is located on the right end. The Si pillar of the lower row is present in a width of an area extended from a contact hole in Y direction in planar view. Then, the Si pillar of the upper row is present in a width of an area extended from a contact hole in Y direction in planar view. In each of the upper row and the lower row, a TiN layer, which is a gate electrode for a loading SGT and a driving SGT, is formed to contact at side surface of entire gate region in a vertical direction between the corresponding Si pillars.

公开(公告)号：US09490362B2

公开(公告)日：2016-11-08

申请号：US14744890

申请日：2015-06-19

Applicant: Unisantis Electronics Singapore Pte. Ltd.

Inventor： Fujio Masuoka ,  Nozomu Harada ,  Hiroki Nakamura ,  Yisuo Li ,  Aashit Ramachandra Kamath ,  Zhixian Chen ,  Teng Soong Phua ,  Xinpeng Wang ,  Patrick Guo-Qiang Lo

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/66666 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/28035 ,  H01L21/28061 ,  H01L21/28238 ,  H01L21/28518 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0692 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/423 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/49 ,  H01L29/4916 ,  H01L29/7827

Abstract: A semiconductor device production method includes a first step of forming a planar silicon layer on a silicon substrate and forming first and second pillar-shaped silicon layers on the planar silicon layer; a second step of forming a gate insulating film around the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, controlling a thickness of the polysilicon film to be smaller than a half of a distance between the first and second pillar-shaped silicon layers, depositing a resist, exposing the polysilicon film on side walls of upper portions of the first and second pillar-shaped semiconductor layers, etching-away the exposed polysilicon film, stripping the third resist, and etching-away the metal film; and a third step of forming a resist for forming a gate line and performing anisotropic etching to form a gate line and first and second gate electrodes.

Abstract translation: 半导体器件制造方法包括在硅衬底上形成平面硅层并在平面硅层上形成第一和第二柱状硅层的第一步骤; 在第一和第二柱状硅层周围形成栅极绝缘膜的第二步骤，在栅极绝缘膜周围形成金属膜和多晶硅膜，控制多晶硅膜的厚度小于一半的距离 在第一和第二柱状硅层之间沉积抗蚀剂，将多晶硅膜暴露在第一和第二柱状半导体层的上部的侧壁上，蚀刻掉暴露的多晶硅膜，剥离第三抗蚀剂，以及 蚀刻掉金属膜; 以及形成用于形成栅极线的抗蚀剂并进行各向异性蚀刻以形成栅极线和第一和第二栅电极的第三步骤。

公开(公告)号：US11862464B2

公开(公告)日：2024-01-02

申请号：US17345543

申请日：2021-06-11

Applicant: Unisantis Electronics Singapore Pte. Ltd.

Inventor： Fujio Masuoka ,  Nozomu Harada ,  Yisuo Li

IPC: H01L21/033 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L21/0338 ,  H01L21/0335 ,  H01L21/0337 ,  H01L29/66666 ,  H01L29/7827 ,  H10B10/12

Abstract: A second band-like mask material layer having a first band-like mask material layer of a same planar shape on its top is formed on a mask material layer on a semiconductor layer. Then, fourth band-like mask material layers having third band-like mask material layers of same planar shape on their top are formed on both side surfaces of the first and second band-like mask material layers. Sixth band-like mask material layers having fifth band-like mask material layers of same planar shape on their top are formed on the outside thereof. Then, an orthogonal band-like mask material layer is formed on the first band-like mask material layer, in a direction orthogonal to a direction in which the first band-like mask material layer extends. Semiconductor pillars are formed on overlapping areas of this orthogonal band-like mask material layer and the second and sixth band-like mask material layers by etching the semiconductor layer. Then, a pillar-shaped semiconductor device is formed with these semiconductor pillars being channels.

公开(公告)号：US09666688B2

公开(公告)日：2017-05-30

申请号：US15263535

申请日：2016-09-13

Applicant: Unisantis Electronics Singapore Pte. Ltd.

Inventor： Fujio Masuoka ,  Nozomu Harada ,  Hiroki Nakamura ,  Yisuo Li ,  Aashit Ramachandra Kamath ,  Zhixian Chen ,  Teng Soong Phua ,  Xinpeng Wang ,  Patrick Guo-Qiang Lo

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L21/02 ,  H01L29/45

CPC classification number: H01L29/66666 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/28035 ,  H01L21/28061 ,  H01L21/28238 ,  H01L21/28518 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0692 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/423 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/49 ,  H01L29/4916 ,  H01L29/7827

Abstract: A semiconductor device production method includes a first step of forming a planar silicon layer on a silicon substrate and forming first and second pillar-shaped silicon layers on the planar silicon layer; a second step of forming a gate insulating film around the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, controlling a thickness of the polysilicon film to be smaller than a half of a distance between the first and second pillar-shaped silicon layers, depositing a resist, exposing the polysilicon film on side walls of upper portions of the first and second pillar-shaped semiconductor layers, etching-away the exposed polysilicon film, stripping the third resist, and etching-away the metal film; and a third step of forming a resist for forming a gate line and performing anisotropic etching to form a gate line and first and second gate electrodes.