公开(公告)号：US20170125297A1

公开(公告)日：2017-05-04

申请号：US14925955

申请日：2015-10-28

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chih-Chung Wang ,  Shih-Yin Hsiao ,  Wen-Fang Lee ,  Nien-Chung Li ,  Shu-Wen Lin

IPC分类号： H01L21/8234 ,  H01L21/28 ,  H01L21/3105 ,  H01L27/088 ,  H01L21/321 ,  H01L29/49 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3213

CPC分类号： H01L21/82345 ,  H01L21/28035 ,  H01L21/31051 ,  H01L21/32115 ,  H01L21/32139 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/4916 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7834

摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a logic region and high-voltage (HV) region; forming a first gate structure on the logic region and a second gate structure on the HV region; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned hard mask on the HV region; and transforming the first gate structure into a metal gate.

公开(公告)号：US09136375B2

公开(公告)日：2015-09-15

申请号：US14085939

申请日：2013-11-21

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chiu-Te Lee ,  Ming-Shun Hsu ,  Ke-Feng Lin ,  Chih-Chung Wang ,  Hsuan-Po Liao ,  Shih-Teng Huang ,  Shu-Wen Lin ,  Su-Hwa Tsai ,  Shih-Yin Hsiao

IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L29/7816 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/1095

摘要： A semiconductor structure is provided. The semiconductor structure comprises a substrate, a deep well formed in the substrate, a first well and a second well formed in the deep well, a gate electrode formed on the substrate and disposed between the first well and the second well, a first isolation, and a second isolation. The second well is spaced apart from the first well. The first isolation extends down from the surface of the substrate and is disposed between the gate electrode and the second well. The second isolation extends down from the surface of the substrate and is adjacent to the first well. A ratio of a depth of the first isolation to a depth of the second isolation is smaller than 1.

摘要翻译： 提供半导体结构。 半导体结构包括衬底，在衬底中形成的深阱，在深阱中形成的第一阱和第二阱，形成在衬底上并设置在第一阱和第二阱之间的栅电极，第一隔离， 和第二个隔离。 第二口井与第一口井隔开。 第一隔离件从衬底的表面向下延伸并且设置在栅电极和第二阱之间。 第二隔离件从衬底的表面向下延伸并与第一阱相邻。 第一隔离深度与第二隔离深度之比小于1。

公开(公告)号：US20150137228A1

公开(公告)日：2015-05-21

申请号：US14085939

申请日：2013-11-21

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chiu-Te Lee ,  Ming-Shun Hsu ,  Ke-Feng Lin ,  Chih-Chung Wang ,  Hsuan-Po Liao ,  Shih-Teng Huang ,  Shu-Wen Lin ,  Su-Hwa Tsai ,  Shih-Yin Hsiao

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L27/088

CPC分类号： H01L29/7816 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/1095

摘要： A semiconductor structure is provided. The semiconductor structure comprises a substrate, a deep well formed in the substrate, a first well and a second well formed in the deep well, a gate electrode formed on the substrate and disposed between the first well and the second well, a first isolation, and a second isolation. The second well is spaced apart from the first well. The first isolation extends down from the surface of the substrate and is disposed between the gate electrode and the second well. The second isolation extends down from the surface of the substrate and is adjacent to the first well. A ratio of a depth of the first isolation to a depth of the second isolation is smaller than 1.

摘要翻译： 提供半导体结构。 半导体结构包括衬底，在衬底中形成的深阱，在深阱中形成的第一阱和第二阱，形成在衬底上并设置在第一阱和第二阱之间的栅电极，第一隔离， 和第二个隔离。 第二口井与第一口井隔开。 第一隔离件从衬底的表面向下延伸并且设置在栅电极和第二阱之间。 第二隔离件从衬底的表面向下延伸并与第一阱相邻。 第一隔离深度与第二隔离深度之比小于1。

公开(公告)号：US10276652B1

公开(公告)日：2019-04-30

申请号：US16005652

申请日：2018-06-11

申请人： UNITED MICROELECTRONICS CORP.

发明人： Cheng-Hua Yang ,  Ke-Feng Lin ,  Ming-Tsung Lee ,  Shih-Teng Huang ,  Chih-Chung Wang ,  Chiu-Te Lee ,  Shu-Wen Lin

IPC分类号： H01L29/06 ,  H01L29/872

摘要： A schottky diode includes a schottky junction, an ohmic junction, a first isolation structure and a plurality of doped regions. The schottky junction includes a first well in a substrate and a first electrode contacting the first well. The ohmic junction includes a junction region in the first well and a second electrode contacting the junction region. The first isolation structure is disposed in the substrate and separates the schottky junction from the ohmic junction. The doped regions are located in the first well and under the schottky junction, wherein the doped regions separating from each other constitute a top-view profile of concentric circles.

公开(公告)号：US20180108528A1

公开(公告)日：2018-04-19

申请号：US15292775

申请日：2016-10-13

申请人： United Microelectronics Corp.

发明人： Shih-Yin Hsiao ,  Shu-Wen Lin ,  Ke-Feng Lin ,  Hsin-Liang Liu ,  Chang-Lin Chen

IPC分类号： H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02

CPC分类号： H01L21/28141 ,  H01L21/28123 ,  H01L21/28211 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/78

摘要： A method for forming a gate oxide layer on a substrate is provided, in which a region of the substrate is defined out by a shallow trench isolation (STI) structure. An oxide layer covers over the substrate and a mask layer with an opening to expose oxide layer corresponding to the region with an interface edge of the STI structure. The method includes forming a silicon spacer on a sidewall of the opening. A cleaning process is performed through the opening to expose the substrate at the region. An oxidation process is performed on the substrate at the region to form the gate oxide layer, wherein the silicon spacer is also oxidized to merge to an edge of the gate oxide layer.

公开(公告)号：US20140225192A1

公开(公告)日：2014-08-14

申请号：US14253365

申请日：2014-04-15

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chiu-Te Lee ,  Ke-Feng Lin ,  Shu-Wen Lin ,  Kun-Huang Yu ,  Chih-Chung Wang ,  Te-Yuan Wu

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/7816 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/407

摘要： A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation. The bottom surface of the second portion of the conductive plug is covered by the isolation.

摘要翻译： 半导体结构包括具有第一导电类型的衬底; 在衬底中形成有第二导电类型的深阱; 具有第一导电类型的第一阱和具有第二导电类型的第二阱都形成在深阱中并且第二阱与第一阱间隔开; 栅电极，形成在所述基板上并且设置在所述第一阱和所述第二阱之间; 从衬底的表面向下延伸并且设置在栅电极和第二阱之间的隔离件; 导电插头，其包括彼此电连接的第一部分和第二部分，并且所述第一部分电连接到所述栅电极，并且所述第二部分穿透所述隔离。 导电插头的第二部分的底表面被隔离层覆盖。

公开(公告)号：US09236471B2

公开(公告)日：2016-01-12

申请号：US14253365

申请日：2014-04-15

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chiu-Te Lee ,  Ke-Feng Lin ,  Shu-Wen Lin ,  Kun-Huang Yu ,  Chih-Chung Wang ,  Te-Yuan Wu

IPC分类号： H01L29/76 ,  H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/7816 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/407

摘要： A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation. The bottom surface of the second portion of the conductive plug is covered by the isolation.

摘要翻译： 半导体结构包括具有第一导电类型的衬底; 在衬底中形成有第二导电类型的深阱; 具有第一导电类型的第一阱和具有第二导电类型的第二阱都形成在深阱中并且第二阱与第一阱间隔开; 栅电极，形成在所述基板上并且设置在所述第一阱和所述第二阱之间; 从衬底的表面向下延伸并且设置在栅电极和第二阱之间的隔离件; 导电插头，其包括彼此电连接的第一部分和第二部分，并且所述第一部分电连接到所述栅电极，并且所述第二部分穿透所述隔离。 导电插头的第二部分的底表面被隔离层覆盖。

公开(公告)号：US09852952B2

公开(公告)日：2017-12-26

申请号：US14925955

申请日：2015-10-28

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chih-Chung Wang ,  Shih-Yin Hsiao ,  Wen-Fang Lee ,  Nien-Chung Li ,  Shu-Wen Lin

IPC分类号： H01L21/8234 ,  H01L21/28 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/321 ,  H01L29/49 ,  H01L29/06 ,  H01L27/088

CPC分类号： H01L21/82345 ,  H01L21/28035 ,  H01L21/31051 ,  H01L21/32115 ,  H01L21/32139 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/4916 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7834

摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a logic region and high-voltage (HV) region; forming a first gate structure on the logic region and a second gate structure on the HV region; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned hard mask on the HV region; and transforming the first gate structure into a metal gate.

公开(公告)号：US09196695B2

公开(公告)日：2015-11-24

申请号：US14273538

申请日：2014-05-08

申请人： UNITED MICROELECTRONICS CORP.

发明人： Kun-Huang Yu ,  Shih-Yin Hsiao ,  Wen-Fang Lee ,  Shu-Wen Lin ,  Kuan-Chuan Chen

IPC分类号： H01L29/76 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/08 ,  H01L21/266 ,  H01L21/28

CPC分类号： H01L29/42368 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28026 ,  H01L21/28158 ,  H01L21/2822 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/401 ,  H01L29/6659 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7834

摘要： The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.

摘要翻译： 本发明提供一种高压金属氧化物半导体（HVMOS）晶体管，其包括衬底，栅极电介质层，栅极电极和源极和漏极区域。 栅介质层设置在基板上，并且包括突出部分和凹陷部分，其中突出部分邻近凹部的两侧设置，并且具有大于凹部的厚度的厚度。 栅电极设置在栅介质层上。 因此，栅极电介质层的突出部分可以保持更高的击穿电压，从而保持电流不通过栅极泄漏。

公开(公告)号：US10297455B2

公开(公告)日：2019-05-21

申请号：US15292775

申请日：2016-10-13

申请人： United Microelectronics Corp.

发明人： Shih-Yin Hsiao ,  Shu-Wen Lin ,  Ke-Feng Lin ,  Hsin-Liang Liu ,  Chang-Lin Chen

IPC分类号： H01L21/8234 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

摘要： A method for forming a gate oxide layer on a substrate is provided, in which a region of the substrate is defined out by a shallow trench isolation (STI) structure. An oxide layer covers over the substrate and a mask layer with an opening to expose oxide layer corresponding to the region with an interface edge of the STI structure. The method includes forming a silicon spacer on a sidewall of the opening. A cleaning process is performed through the opening to expose the substrate at the region. An oxidation process is performed on the substrate at the region to form the gate oxide layer, wherein the silicon spacer is also oxidized to merge to an edge of the gate oxide layer.