公开(公告)号：US20220068766A1

公开(公告)日：2022-03-03

申请号：US17521805

申请日：2021-11-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Pin Hsu ,  Chih-Jung Wang ,  Chu-Chun Chang ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Purakh Raj Verma

IPC: H01L23/482 ,  H01L21/02 ,  H01L21/762 ,  H01L21/768 ,  H01L23/485

Abstract: A semiconductor structure with an air gap includes a dielectric stack having a first dielectric layer on a substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer. A first conductive layer and a second conductive layer are disposed in the dielectric stack. The first conductive layer and the second conductive layer are coplanar. A cross-like-shaped air gap is disposed in the dielectric stack between the first and second conductive layers. An oxide layer is disposed on a sidewall of the second dielectric layer within the cross-like-shaped air gap.

公开(公告)号：US20240203785A1

公开(公告)日：2024-06-20

申请号：US18179377

申请日：2023-03-07

Applicant: United Microelectronics Corp.

Inventor： Ching-Pin Hsu ,  Shih Hung Yang ,  Chu Chun Chang ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06

CPC classification number: H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5283 ,  H01L29/0649

Abstract: A semiconductor device includes a conductive structure, a first dielectric layer, a second dielectric layer and a liner layer. The conductive structure is located on a substrate. The first dielectric layer covers the conductive structure and the substrate. The second dielectric layer is located on the first dielectric layer. An air gap is present in the first dielectric layer and the second dielectric layer, and is located above the conductive structure. The liner layer covers and surrounds a middle portion of the air gap.

公开(公告)号：US10658173B2

公开(公告)日：2020-05-19

申请号：US16039284

申请日：2018-07-18

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen ,  Ching-Pin Hsu

IPC: H01L21/02 ,  H01L21/3213 ,  H01L21/67 ,  H01L21/3065 ,  H01L27/108

Abstract: A method for fabricating a semiconductor structure on a semiconductor wafer is disclosed. A semiconductor wafer having a first region, a second region, and a wafer bevel region is provided. The wafer bevel region has a silicon surface. A first semiconductor structure is formed in the first region and a second semiconductor structure is formed in the second region. The semiconductor wafer is subjected to a bevel plasma treatment to form a blocking layer only in the wafer bevel region. A silicidation process is then performed to form a silicide layer only in the first region and the second region.

公开(公告)号：US20140315365A1

公开(公告)日：2014-10-23

申请号：US13866456

申请日：2013-04-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Chiang Chen ,  Jiunn-Hsiung Liao ,  Hsuan-Hsu Chen ,  Feng-Yi Chang ,  Chieh-Te Chen ,  Shang-Yuan Tsai ,  Ching-Pin Hsu

IPC: H01L29/423 ,  H01L29/66

CPC classification number: H01L29/42372 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/823828 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of forming a semiconductor device is provided. At least one gate structure including a dummy gate is formed on a substrate. A contact etch stop layer and a dielectric layer are formed to cover the gate structure. A portion of the contact etch stop layer and a portion of the dielectric layer are removed to expose the top of the gate structure. A dry etching process is performed to remove a portion of the dummy gate of the gate structure. A hydrogenation treatment is performed to the surface of the remaining dummy gate. A wet etching process is performed to remove the remaining dummy gate and thereby form a gate trench.

Abstract translation: 提供一种形成半导体器件的方法。 在基板上形成包括虚拟栅极的至少一个栅极结构。 形成接触蚀刻停止层和电介质层以覆盖栅极结构。 接触蚀刻停止层的一部分和电介质层的一部分被去除以暴露栅极结构的顶部。 执行干蚀刻处理以去除栅极结构的虚拟栅极的一部分。 对剩余的虚拟栅极的表面进行氢化处理。 执行湿蚀刻处理以去除剩余的虚拟栅极，从而形成栅极沟槽。

公开(公告)号：US08785283B2

公开(公告)日：2014-07-22

申请号：US13705183

申请日：2012-12-05

Applicant: United Microelectronics Corp.

Inventor： Chieh-Te Chen ,  Feng-Yi Chang ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Ching-Pin Hsu

IPC: H01L21/336 ,  H01L29/66

CPC classification number: H01L21/76816 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method for forming a semiconductor structure having a metal connect. A substrate is provided, and a transistor and a first ILD layer are formed thereon. A first contact plug is formed in the first ILD layer to electrically connect the source/drain region. A second ILD layer and a third ILD layer are formed on the first ILD layer. A first opening above the gate and a second opening above the first contact plug are formed, wherein a depth of the first contact plug is deeper than that of the second opening. Next, the first opening and the second opening are deepened. Lastly, a metal layer is filled into the first opening and the second opening to respectively form a first metal connect and a second metal connect.

Abstract translation: 本发明提供一种形成具有金属连接的半导体结构的方法。 提供衬底，并在其上形成晶体管和第一ILD层。 第一接触插塞形成在第一ILD层中以电连接源极/漏极区域。 在第一ILD层上形成第二ILD层和第三ILD层。 形成在栅极上方的第一开口和在第一接触插塞上方的第二开口，其中第一接触插塞的深度比第二开口的深度深。 接下来，加深第一开口和第二开口。 最后，将金属层填充到第一开口和第二开口中，以分别形成第一金属连接和第二金属连接。

公开(公告)号：US11848253B2

公开(公告)日：2023-12-19

申请号：US17521805

申请日：2021-11-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Pin Hsu ,  Chih-Jung Wang ,  Chu-Chun Chang ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Purakh Raj Verma

IPC: H01L23/482 ,  H01L21/02 ,  H01L21/762 ,  H01L21/768 ,  H01L23/485

CPC classification number: H01L23/4821 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/7682 ,  H01L21/76243 ,  H01L23/485

Abstract: A semiconductor structure with an air gap includes a dielectric stack having a first dielectric layer on a substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer. A first conductive layer and a second conductive layer are disposed in the dielectric stack. The first conductive layer and the second conductive layer are coplanar. A cross-like-shaped air gap is disposed in the dielectric stack between the first and second conductive layers. An oxide layer is disposed on a sidewall of the second dielectric layer within the cross-like-shaped air gap.

公开(公告)号：US20140154852A1

公开(公告)日：2014-06-05

申请号：US13705183

申请日：2012-12-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chieh-Te Chen ,  Feng-Yi Chang ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Ching-Pin Hsu

IPC: H01L29/66

CPC classification number: H01L21/76816 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method for forming a semiconductor structure having a metal connect. A substrate is provided, and a transistor and a first ILD layer are formed thereon. A first contact plug is formed in the first ILD layer to electrically connect the source/drain region. A second ILD layer and a third ILD layer are formed on the first ILD layer. A first opening above the gate and a second opening above the first contact plug are formed, wherein a depth of the first contact plug is deeper than that of the second opening. Next, the first opening and the second opening are deepened. Lastly, a metal layer is filled into the first opening and the second opening to respectively form a first metal connect and a second metal connect.

Abstract translation: 本发明提供一种形成具有金属连接的半导体结构的方法。 提供衬底，并在其上形成晶体管和第一ILD层。 第一接触插塞形成在第一ILD层中以电连接源极/漏极区域。 在第一ILD层上形成第二ILD层和第三ILD层。 形成在栅极上方的第一开口和在第一接触插塞上方的第二开口，其中第一接触插塞的深度比第二开口的深度深。 接下来，加深第一开口和第二开口。 最后，将金属层填充到第一开口和第二开口中，以分别形成第一金属连接和第二金属连接。

公开(公告)号：US20140038399A1

公开(公告)日：2014-02-06

申请号：US14054839

申请日：2013-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Feng-Yi Chang ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shang-Yuan Tsai ,  Chih-Wen Feng ,  Shui-Yen Lu ,  Ching-Pin Hsu

IPC: H01L21/308

CPC classification number: H01L21/308 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816

Abstract: A method for fabricating an aperture is disclosed. The method includes the steps of: forming a hard mask containing carbon on a surface of a semiconductor substrate; and using a non-oxygen element containing gas to perform a first etching process for forming a first aperture in the hard mask. Before forming the hard mask, a gate which includes a contact etch stop layer and a dielectric layer is formed on the semiconductor substrate.

Abstract translation: 公开了一种制造孔的方法。 该方法包括以下步骤：在半导体衬底的表面上形成含有碳的硬掩模; 并且使用含有气体的非氧元素进行用于在硬掩模中形成第一孔的第一蚀刻工艺。 在形成硬掩模之前，在半导体衬底上形成包括接触蚀刻停止层和电介质层的栅极。

公开(公告)号：US11205609B2

公开(公告)日：2021-12-21

申请号：US16835349

申请日：2020-03-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Pin Hsu ,  Chih-Jung Wang ,  Chu-Chun Chang ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Purakh Raj Verma

IPC: H01L23/482 ,  H01L21/02 ,  H01L21/762 ,  H01L21/768 ,  H01L23/485

Abstract: A semiconductor structure with an air gap includes a dielectric stack having a first dielectric layer on a substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer. A first conductive layer and a second conductive layer are disposed in the dielectric stack. The first conductive layer and the second conductive layer are coplanar. A cross-like-shaped air gap is disposed in the dielectric stack between the first and second conductive layers. An oxide layer is disposed on a sidewall of the second dielectric layer within the cross-like-shaped air gap.

公开(公告)号：US20200020524A1

公开(公告)日：2020-01-16

申请号：US16039284

申请日：2018-07-18

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen ,  Ching-Pin Hsu

IPC: H01L21/02 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/3213

Abstract: A method for fabricating a semiconductor structure on a semiconductor wafer is disclosed. A semiconductor wafer having a first region, a second region, and a wafer bevel region is provided. The wafer bevel region has a silicon surface. A first semiconductor structure is formed in the first region and a second semiconductor structure is formed in the second region. The semiconductor wafer is subjected to a bevel plasma treatment to form a blocking layer only in the wafer bevel region. A silicidation process is then performed to form a silicide layer only in the first region and the second region.