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公开(公告)号：US10199258B2
公开(公告)日：2019-02-05
申请号：US15384940
申请日：2016-12-20
Inventor： Chieh-Te Chen , Hsien-Shih Chu , Ming-Feng Kuo , Fu-Che Lee , Chien-Ting Ho , Chiung-Lin Hsu , Feng-Yi Chang , Yi-Wang Zhan , Li-Chiang Chen , Chien-Cheng Tsai , Chin-Hsin Chiu
IPC: H01L21/762 , H01L21/308
Abstract: A method of fabricating an isolation structure is provided. A first oxide layer and a first, second, and third hard mask layers are formed on a substrate. A patterned third hard mask layer is formed. Second oxide layers are formed on sidewalls of the patterned third hard mask layer and a fourth hard mask layer is formed between the second oxide layers. The second oxide layers and the second hard mask layer are removed using the patterned third hard mask layer and the fourth hard mask layer as a mask, to form a patterned second hard mask layer. The patterned third hard mask layer and the fourth hard mask layer are removed. A portion of the patterned second hard mask layer is removed to form trench patterns. A patterned first hard mask layer and first oxide layer, and trenches located in the substrate are defined. An isolation material is formed.
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公开(公告)号：US20180342425A1
公开(公告)日：2018-11-29
申请号：US16038196
申请日：2018-07-18
Inventor： Feng-Yi Chang , Shih-Fang Tzou , Yu-Cheng Tung , Ming-Feng Kuo , Li-Chiang Chen
IPC: H01L21/8234 , H01L27/108
Abstract: A semiconductor device includes a first gate structure in a substrate and a second gate structure in the substrate and adjacent to the first gate structure. Preferably, a top surface of the first gate structure and a top surface of the second gate structure are lower than a top surface of the substrate and a number of work function metal layers in the first gate structure and the second gate structure are different.
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公开(公告)号：US20140315365A1
公开(公告)日：2014-10-23
申请号：US13866456
申请日：2013-04-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Li-Chiang Chen , Jiunn-Hsiung Liao , Hsuan-Hsu Chen , Feng-Yi Chang , Chieh-Te Chen , Shang-Yuan Tsai , Ching-Pin Hsu
IPC: H01L29/423 , H01L29/66
CPC classification number: H01L29/42372 , H01L21/28088 , H01L21/32134 , H01L21/32135 , H01L21/823828 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7848
Abstract: A method of forming a semiconductor device is provided. At least one gate structure including a dummy gate is formed on a substrate. A contact etch stop layer and a dielectric layer are formed to cover the gate structure. A portion of the contact etch stop layer and a portion of the dielectric layer are removed to expose the top of the gate structure. A dry etching process is performed to remove a portion of the dummy gate of the gate structure. A hydrogenation treatment is performed to the surface of the remaining dummy gate. A wet etching process is performed to remove the remaining dummy gate and thereby form a gate trench.
Abstract translation: 提供一种形成半导体器件的方法。 在基板上形成包括虚拟栅极的至少一个栅极结构。 形成接触蚀刻停止层和电介质层以覆盖栅极结构。 接触蚀刻停止层的一部分和电介质层的一部分被去除以暴露栅极结构的顶部。 执行干蚀刻处理以去除栅极结构的虚拟栅极的一部分。 对剩余的虚拟栅极的表面进行氢化处理。 执行湿蚀刻处理以去除剩余的虚拟栅极，从而形成栅极沟槽。
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公开(公告)号：US10062613B1
公开(公告)日：2018-08-28
申请号：US15611759
申请日：2017-06-01
Inventor： Feng-Yi Chang , Shih-Fang Tzou , Yu-Cheng Tung , Ming-Feng Kuo , Li-Chiang Chen
IPC: H01L27/108 , H01L29/51 , H01L29/78 , H01L21/8234
CPC classification number: H01L21/823456 , H01L21/82345 , H01L27/10823 , H01L27/10876 , H01L27/10891
Abstract: A method for fabricating semiconductor device includes the steps of: forming a first trench and a second trench in a substrate; forming a first work function metal layer in the first trench and the second trench; forming a patterned mask to cover the second trench; removing the first work function metal layer from the first trench; forming a second work function metal layer in the first trench and the second trench; and forming a conductive layer in the first trench and the second trench to form a first gate structure and a second gate structure.
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公开(公告)号：US09023708B2
公开(公告)日：2015-05-05
申请号：US13866456
申请日：2013-04-19
Applicant: United Microelectronics Corp.
Inventor： Li-Chiang Chen , Jiunn-Hsiung Liao , Hsuan-Hsu Chen , Feng-Yi Chang , Chieh-Te Chen , Shang-Yuan Tsai , Ching-Pin Hsu
IPC: H01L21/336 , H01L29/423 , H01L29/66
CPC classification number: H01L29/42372 , H01L21/28088 , H01L21/32134 , H01L21/32135 , H01L21/823828 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7848
Abstract: A method of forming a semiconductor device is provided. At least one gate structure including a dummy gate is formed on a substrate. A contact etch stop layer and a dielectric layer are formed to cover the gate structure. A portion of the contact etch stop layer and a portion of the dielectric layer are removed to expose the top of the gate structure. A dry etching process is performed to remove a portion of the dummy gate of the gate structure. A hydrogenation treatment is performed to the surface of the remaining dummy gate. A wet etching process is performed to remove the remaining dummy gate and thereby form a gate trench.
Abstract translation: 提供一种形成半导体器件的方法。 在基板上形成包括虚拟栅极的至少一个栅极结构。 形成接触蚀刻停止层和电介质层以覆盖栅极结构。 接触蚀刻停止层的一部分和电介质层的一部分被去除以暴露栅极结构的顶部。 执行干蚀刻处理以去除栅极结构的虚拟栅极的一部分。 对剩余的虚拟栅极的表面进行氢化处理。 执行湿蚀刻处理以去除剩余的虚拟栅极，从而形成栅极沟槽。
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Patent Agency Ranking
公开(公告)号：US20190318929A1
公开(公告)日：2019-10-17
申请号：US15972223
申请日：2018-05-06
Inventor： Yu-Chen Chuang , Fu-Che Lee , Ming-Feng Kuo , Cheng-Yu Wang , Hsien-Shih Chu , Li-Chiang Chen
IPC: H01L21/033
Abstract: A patterning method includes the following steps. A hard mask layer is formed on a substrate. Mandrels are formed on the hard mask layer. Mask patterns are formed on the mandrels. Each of the mask patterns is formed on one of the mandrels. Spacers are formed on the hard mask layer. Each of the spacers is formed on a sidewall of one of the mandrels and on a sidewall of one of the mask patterns. A cover layer covering the hard mask layer, the spacers and the mask patterns is formed. A planarization process is performed to remove the cover layer on the mask patterns and the spacer and remove the mask patterns. A part of the cover layer remains between the spacers after the planarization process. The mandrels and the cover layer are removed after the planarization process.
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公开(公告)号：US20180108563A1
公开(公告)日：2018-04-19
申请号：US15384940
申请日：2016-12-20
Inventor： Chieh-Te Chen , Hsien-Shih Chu , Ming-Feng Kuo , Fu-Che Lee , Chien-Ting Ho , Chiung-Lin Hsu , Feng-Yi Chang , Yi-Wang Zhan , Li-Chiang Chen , Chien-Cheng Tsai , Chin-Hsin Chiu
IPC: H01L21/762 , H01L21/308
CPC classification number: H01L21/76224 , H01L21/3081 , H01L21/762
Abstract: A method of fabricating an isolation structure is provided. A first oxide layer and a first, second, and third hard mask layers are formed on a substrate. A patterned third hard mask layer is formed. Second oxide layers are formed on sidewalls of the patterned third hard mask layer and a fourth hard mask layer is formed between the second oxide layers. The second oxide layers and the second hard mask layer are removed using the patterned third hard mask layer and the fourth hard mask layer as a mask, to form a patterned second hard mask layer. The patterned third hard mask layer and the fourth hard mask layer are removed. A portion of the patterned second hard mask layer is removed to form trench patterns. A patterned first hard mask layer and first oxide layer, and trenches located in the substrate are defined. An isolation material is formed.
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公开(公告)号：US09887088B1
公开(公告)日：2018-02-06
申请号：US15452743
申请日：2017-03-08
Inventor： Feng-Yi Chang , Shih-Fang Tzou , Fu-Che Lee , Ming-Feng Kuo , Li-Chiang Chen
IPC: H01L21/28 , H01L21/3213
CPC classification number: H01L21/28088 , H01L21/32135
Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region defined thereon; forming a trench in the substrate; forming a barrier layer in the trench; forming a conductive layer on the barrier layer; performing a first etching process to remove part of the conductive layer; and performing a second etching process to remove part of the barrier layer. Preferably, the second etching process comprises a non-plasma etching process.
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公开(公告)号：US20150126015A1
公开(公告)日：2015-05-07
申请号：US14583122
申请日：2014-12-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chieh-Te Chen , Yi-Po Lin , Jiunn-Hsiung Liao , Shui-Yen Lu , Li-Chiang Chen
IPC: H01L49/02
CPC classification number: H01L28/20 , H01L21/76897 , H01L27/0629 , H01L28/24 , H01L29/66545
Abstract: A semiconductor structure includes a substrate, a resist layer, a dielectric material, two U-shaped metal layers and two metals. The substrate has an isolation structure. The resist layer is located on the isolation structure. The dielectric material is located on the resist layer. Two U-shaped metal layers are located at the two sides of the dielectric material and on the resist layer. Two metals are respectively located on the two U-shaped metal layers. This way a semiconductor process for forming said semiconductor structure is provided.
Abstract translation: 半导体结构包括基板，抗蚀剂层，电介质材料，两个U形金属层和两种金属。 衬底具有隔离结构。 抗蚀剂层位于隔离结构上。 介电材料位于抗蚀剂层上。 两个U形金属层位于电介质材料的两侧和抗蚀剂层上。 两个金属分别位于两个U形金属层上。 以这种方式提供了用于形成所述半导体结构的半导体工艺。
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公开(公告)号：US10937701B2
公开(公告)日：2021-03-02
申请号：US16038196
申请日：2018-07-18
Inventor： Feng-Yi Chang , Shih-Fang Tzou , Yu-Cheng Tung , Ming-Feng Kuo , Li-Chiang Chen
IPC: H01L27/108 , H01L21/8234
Abstract: A semiconductor device includes a first gate structure in a substrate and a second gate structure in the substrate and adjacent to the first gate structure. Preferably, a top surface of the first gate structure and a top surface of the second gate structure are lower than a top surface of the substrate and a number of work function metal layers in the first gate structure and the second gate structure are different.
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