公开(公告)号：US06488823B1

公开(公告)日：2002-12-03

申请号：US09423470

申请日：1999-11-04

申请人： Tony Chiang ,  Peijun Ding ,  Barry L. Chin ,  Bingxi Sun

发明人： Tony Chiang ,  Peijun Ding ,  Barry L. Chin ,  Bingxi Sun

IPC分类号： C23C1434

CPC分类号： C23C14/345 ,  C23C14/0036 ,  C23C14/0641 ,  C23C14/16 ,  C23C14/3492 ,  C23C14/358 ,  C23C14/5833 ,  H01L21/2855 ,  H01L21/76838 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76864 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure pertains to our discovery that residual stress residing in a tantalum film or tantalum nitride film can be controlled (tuned) during deposition by adjusting at least two particular process variables which have counteracting effects on the residual film stress. By tuning individual film stresses within a film stack, it is possible to balance stresses within the stack. Process variables of particular interest include: power to the sputtering target process chamber pressure (i.e., the concentration of various gases and ions present in the chamber); substrate DC offset bias voltage (typically an increase in the AC applied substrate bias power); power to an ionization source (typically a coil); and temperature of the substrate upon which the film is deposited. The process chamber pressure and the substrate offset bias most significantly affect the film tensile and compressive stress components, respectively. The most advantageous tuning of a sputtered film is achieved using high density plasma sputter deposition, which provides for particular control over the ion bombardment of the depositing film surface. When the tantalum or tantalum nitride film is deposited using high density plasma sputtering, power to the ionization source can be varied for stress tuning of the film. We have been able to reduce the residual stress in tantalum or tantalum nitride films deposited using high density plasma sputtering to between about 6×10+9 dynes/cm2 and about −6×10+9 dynes/cm2 using techniques described herein.

摘要翻译： 本公开涉及我们的发现，即通过调节对剩余膜应力具有抵消作用的至少两个特定工艺变量，可以在沉积期间控制（调整）驻留在钽膜或氮化钽膜中的残余应力。 通过调整薄膜叠层内的各个薄膜应力，可以平衡叠层内的应力。 特别感兴趣的过程变量包括：溅射靶处理室压力的功率（即存在于室中的各种气体和离子的浓度）; 衬底DC偏移偏置电压（通常为施加衬底偏置功率的AC增加）; 电源（通常为线圈）; 以及沉积膜的基板的温度。 处理室压力和基板偏移偏压分别最显着地影响膜的拉伸和压应力分量。 使用高密度等离子体溅射沉积来实现溅射膜的最有利的调谐，其提供对沉积膜表面的离子轰击的特定控制。 当使用高密度等离子体溅射沉积钽或氮化钽膜时，电离源的功率可以改变以用于膜的应力调谐。 使用本文所述的技术，我们已经能够将使用高密度等离子体溅射沉积的钽或氮化钽膜中的残余应力减小到约6×10 9 + 9达因/ cm 2和约-6×10 9达因/ cm 2之间。

公开(公告)号：US6160315A

公开(公告)日：2000-12-12

申请号：US478721

申请日：2000-01-06

申请人： Tony Chiang ,  Peijun Ding ,  Barry Chin ,  Imran Hashim ,  Bingxi Sun

发明人： Tony Chiang ,  Peijun Ding ,  Barry Chin ,  Imran Hashim ,  Bingxi Sun

IPC分类号： C23C14/02 ,  C23C14/16 ,  C23C16/02 ,  C23C16/06 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76834 ,  C23C14/024 ,  C23C14/025 ,  C23C14/16 ,  C23C14/165 ,  C23C16/0281 ,  C23C16/06 ,  H01L21/2855 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A copper via structure formed when copper and a small amount of an alloying metal such as magnesium or aluminum are cosputtered onto a substrate having oxide on at least a portion of its surface. Either the wafer is held at an elevated temperature during deposition or the sputtered film is annealed without the wafer being exposed to ambient. Due to the high temperature, the alloying metal diffuses to the surface. If a surface is exposed to a low partial pressure of oxygen or contacts silicon dioxide, the magnesium or aluminum forms a thin stable oxide but also extends into the oxide a distance of about 100 nm. The alloying metal oxide having a thickness of about 6 nm on the oxide sidewalls encapsulates the copper layer to provide a barrier against copper migration, to form an adhesion layer over silicon dioxide, and to act as a seed layer for the later growth of copper, for example, by electroplating.

摘要翻译： 当铜和少量的合金金属如镁或铝形成的铜通孔结构在其表面的至少一部分上被分散在具有氧化物的基底上。 在沉积期间晶片保持在升高的温度下，或者溅射膜被退火而晶片不暴露于环境中。 由于高温，合金金属扩散到表面。 如果表面暴露于低的氧分压或接触二氧化硅，则镁或铝形成薄的稳定氧化物，但也延伸到氧化物中约100nm的距离。 在氧化物侧壁上具有约6nm厚度的合金化金属氧化物封装铜层以提供阻挡铜迁移的屏障，以形成二氧化硅以上的粘合层，并且用作后续生长铜的种子层， 例如，通过电镀。

公开(公告)号：US06387805B2

公开(公告)日：2002-05-14

申请号：US08878143

申请日：1997-06-18

申请人： Peijun Ding ,  Tony Chiang ,  Imran Hashim ,  Bingxi Sun ,  Barry Chin

发明人： Peijun Ding ,  Tony Chiang ,  Imran Hashim ,  Bingxi Sun ,  Barry Chin

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  C23C14/024 ,  C23C14/025 ,  C23C14/16 ,  C23C14/165 ,  C23C16/0281 ,  C23C16/06 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76867 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A copper metallization structure and its method of formation in which a layer of a copper alloy, such as Cu—Mg or Cu—Al is deposited over a silicon oxide based dielectric layer and a substantially pure copper layer is deposited over the copper alloy layer. The copper alloy layer serves as a seed or wetting layer for subsequent filling of via holes and trenches with substantially pure copper. Preferably, the copper alloy is deposited cold in a sputter process, but, during the deposition of the pure copper layer or afterwards in a separate annealing step, the temperature is raised sufficiently high to cause the alloying element of the copper alloy to migrate to the dielectric layer and form a barrier there against diffusion of copper into and through the dielectric layer. This barrier also promotes adhesion of the alloy layer to the dielectric layer, thereby forming a superior wetting and seed layer for subsequent copper full-fill techniques. Filling of the alloy-lined feature can be accomplished using PVD, CVD, or electro/electroless plating.

摘要翻译： 在铜合金层上沉积铜基金属化结构及其形成方法，其中在氧化硅基介电层和基本上纯的铜层上沉积诸如Cu-Mg或Cu-Al的铜合金层。 铜合金层用作种子或润湿层，用于随后用基本上纯的铜填充通孔和沟槽。 优选地，铜合金在溅射过程中冷沉积，但是在纯铜层沉积期间或之后在单独的退火步骤中，温度升高到足够高以使铜合金的合金元素迁移到 电介质层，并形成阻挡铜，以扩散到介电层中并穿过介电层。 该屏障还促进了合金层对电介质层的粘附，从而形成了用于随后的铜全填充技术的优异的润湿和种子层。 可以使用PVD，CVD或电/无电镀来完成合金衬里特征的填充。

公开(公告)号：US06313033B1

公开(公告)日：2001-11-06

申请号：US09362923

申请日：1999-07-27

申请人： Tony Chiang ,  Bingxi Sun ,  Suraj Rengarajan ,  Peijun Ding ,  Barry Chin

发明人： Tony Chiang ,  Bingxi Sun ,  Suraj Rengarajan ,  Peijun Ding ,  Barry Chin

IPC分类号： H01L2144

CPC分类号： H01L27/1087 ,  H01L21/2855 ,  H01L21/76843 ,  H01L28/40 ,  H01L28/56 ,  H01L28/75

摘要： The invention provides a method for forming a microelectronic device comprising: forming a first electrode; depositing an adhesion layer over the first electrode utilizing high density plasma physical vapor deposition, wherein the adhesion layer comprises a material selected from Ta, TaNx, W, WNx, Ta/TaNx, W/WNx, and combinations thereof, depositing a dielectric layer over the adhesion layer; and forming a second electrode over the dielectric layer. The invention also provides a microelectronic device comprising: a first electrode; a second electrode; a dielectric layer disposed between the first and second electrodes; and an adhesion layer disposed between the first electrode and the dielectric layer, wherein the adhesion layer comprises a material selected from Ta, TaNx, W, WNx, Ta/TaNx, W/WNx, and combinations thereof.

摘要翻译： 本发明提供一种形成微电子器件的方法，包括：形成第一电极; 使用高密度等离子体物理气相沉积在第一电极上沉积粘合层，其中粘合层包括选自Ta，TaNx，W，WNx，Ta / TaNx，W / WNx的材料及其组合，将介电层沉积在 粘合层; 以及在所述电介质层上形成第二电极。 本发明还提供了一种微电子器件，包括：第一电极; 第二电极; 设置在所述第一和第二电极之间的电介质层; 以及设置在第一电极和电介质层之间的粘合层，其中粘合层包括选自Ta，TaNx，W，WNx，Ta / TaNx，W / WNx的材料及其组合。

公开(公告)号：US06066892A

公开(公告)日：2000-05-23

申请号：US79107

申请日：1998-05-14

申请人： Peijun Ding ,  Tony Chiang ,  Imran Hashim ,  Bingxi Sun ,  Barry Chin

发明人： Peijun Ding ,  Tony Chiang ,  Imran Hashim ,  Bingxi Sun ,  Barry Chin

IPC分类号： H01L21/28 ,  C23C14/02 ,  C23C14/16 ,  C23C16/02 ,  C23C16/06 ,  H01L21/203 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L29/45

CPC分类号： H01L21/76843 ,  C23C14/024 ,  C23C14/025 ,  C23C14/16 ,  C23C14/165 ,  C23C16/0281 ,  C23C16/06 ,  H01L21/28556 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76867 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/53233 ,  H01L23/53238 ,  H01L21/2855 ,  H01L2924/0002

摘要： A copper metallization structure in which a layer of a copper alloy, such as Cu--Mg or Cu--Al is deposited over a silicon oxide based dielectric layer and a substantially pure copper layer is deposited over the copper alloy layer. The copper alloy layer serves as a seed or wetting layer for subsequent filling of via holes and trenches with substantially pure copper. Preferred examples of the alloying elements and their atomic alloying percentage include magnesium between 0.05 and 6% and aluminum between 0.05 and 0.3%. Further examples include boron, tantalum, tellurium, and titanium. Preferably, the copper alloy is deposited cold in a sputter process, but, during the deposition of the pure copper layer or afterwards in a separate annealing step, the temperature is raised sufficiently high to cause the alloying element of the copper alloy to migrate to the dielectric layer and form a barrier there against diffusion of copper into and through the dielectric layer. This barrier also promotes adhesion of the alloy layer to the dielectric layer, thereby forming a superior wetting and seed layer for subsequent copper full-fill techniques. Filling of the alloy-lined feature can be accomplished using PVD, CVD, or electro/electroless plating.

摘要翻译： 在铜合金层上沉积铜基金属化结构，其中在氧化硅基介电层和基本上纯的铜层上沉积诸如Cu-Mg或Cu-Al的铜合金层。 铜合金层用作种子或润湿层，用于随后用基本上纯的铜填充通孔和沟槽。 合金元素的优选实例及其原子合金化百分比包括0.05至6％的镁和0.05-0.3％的铝。 其他实例包括硼，钽，碲和钛。 优选地，铜合金在溅射过程中冷沉积，但是在纯铜层沉积期间或之后在单独的退火步骤中，温度升高到足够高以使铜合金的合金元素迁移到 电介质层，并形成阻挡铜，以扩散到介电层中并穿过介电层。 该屏障还促进了合金层对电介质层的粘附，从而形成了用于随后的铜全填充技术的优异的润湿和种子层。 可以使用PVD，CVD或电/无电镀来完成合金衬里特征的填充。

公开(公告)号：US6037257A

公开(公告)日：2000-03-14

申请号：US853191

申请日：1997-05-08

申请人： Tony Chiang ,  Peijun Ding ,  Barry Chin ,  Imran Hashim ,  Bingxi Sun

发明人： Tony Chiang ,  Peijun Ding ,  Barry Chin ,  Imran Hashim ,  Bingxi Sun

IPC分类号： C23C14/02 ,  C23C14/16 ,  C23C16/02 ,  C23C16/06 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532 ,  H01L21/4763 ,  H01L21/44 ,  H01L23/48

CPC分类号： H01L21/76834 ,  C23C14/024 ,  C23C14/025 ,  C23C14/16 ,  C23C14/165 ,  C23C16/0281 ,  C23C16/06 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/53233 ,  H01L23/53238 ,  H01L21/2855 ,  H01L2924/0002

摘要： Copper and a small amount of an alloying metal such as magnesium or aluminum are cosputtered onto a substrate having oxide on at least a portion of its surface. Either the wafer is held at an elevated temperature during deposition or the sputtered film is annealed without the wafer being exposed to ambient. Due to the high temperature, the alloying metal diffuses to the surface. If a surface is exposed to a low partial pressure of oxygen or contacts silicon dioxide, the magnesium or aluminum forms a thin stable oxide. The alloying metal oxide encapsulates the copper layer to provide a barrier against copper migration, to form an adhesion layer over silicon dioxide, and to act as a seed layer for the later growth of copper, for example, by electroplating.

摘要翻译： 将铜和少量合金化金属如镁或铝分散在其表面的至少一部分上具有氧化物的衬底上。 在沉积期间晶片保持在升高的温度下，或者溅射膜被退火而晶片不暴露于环境中。 由于高温，合金金属扩散到表面。 如果表面暴露于低的氧分压或接触二氧化硅，则镁或铝形成薄的稳定的氧化物。 合金化金属氧化物封装铜层以提供阻挡铜迁移的屏障，以形成二氧化硅以上的粘合层，并且作为例如通过电镀的铜的后续生长的种子层。

公开(公告)号：US20090053888A1

公开(公告)日：2009-02-26

申请号：US12288540

申请日：2008-10-20

申请人： Peijun Ding ,  Zheng Xu ,  Hong Zhang ,  Xianmin Tang ,  Praburam Gopalraja ,  Suraj Rengarajan ,  John C. Forster ,  Jianming Fu ,  Tony Chiang ,  Gongda Yao ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara

发明人： Peijun Ding ,  Zheng Xu ,  Hong Zhang ,  Xianmin Tang ,  Praburam Gopalraja ,  Suraj Rengarajan ,  John C. Forster ,  Jianming Fu ,  Tony Chiang ,  Gongda Yao ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara

IPC分类号： H01L21/4763 ,  H01L21/31

CPC分类号： H01L21/02183 ,  C23C14/0641 ,  C23C14/165 ,  C23C14/541 ,  C23C14/5806 ,  H01L21/02266 ,  H01L21/2855 ,  H01L21/318 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76876

摘要： A method of depositing a duffusion barrier layer with overlying conductive layer or fill which lowers resistivity of a semiconductor device interconnect. The lower resistivity is achieved by inducing the formation of alpha tantalum within a tantalum-comprising barrier layer.

摘要翻译： 一种用覆盖的导电层或填充物沉积具有降低半导体器件互连电阻率的渗透阻挡层的方法。 通过诱导在含钽隔离层内形成α钽来实现较低的电阻率。

公开(公告)号：US06793779B2

公开(公告)日：2004-09-21

申请号：US10369856

申请日：2003-02-20

申请人： Peijun Ding ,  Tony Chiang ,  Barry L. Chin

发明人： Peijun Ding ,  Tony Chiang ,  Barry L. Chin

IPC分类号： C23C1434

CPC分类号： H01L21/76877 ,  H01L21/2855

摘要： A method of filling trenches or vias on a semiconductor workpiece surface with copper using sputtering techniques. A copper wetting layer and a copper fill layer may both be applied by sputtering techniques. The thin wetting layer of copper is applied at a substrate surface temperature ranging between about 20° C. to about 250° C., and subsequently the temperature of the substrate is increased, with the application of the sputtered copper fill layer beginning at above at least about 200° C. and continuing while the substrate temperature is increased to a temperature as high as about 600° C. Preferably the substrate temperature during application of the sputtered fill layer ranges between about 300° C. and about 500° C.

摘要翻译： 使用溅射技术用铜填充半导体工件表面上的沟槽或通孔的方法。 铜浸润层和铜填充层都可以通过溅射技术施加。 在约20℃至约250℃范围内的衬底表面温度下施加铜的薄润湿层，随后随着溅射铜填充层的应用从上方开始施加，衬底的温度升高 至少约200℃，并且在衬底温度升高至高达约600℃的温度下继续进行。优选地，溅射填充层施加期间的衬底温度范围为约300℃至约500℃。

公开(公告)号：US09390970B2

公开(公告)日：2016-07-12

申请号：US11733671

申请日：2007-04-10

申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： H01L21/768 ,  C23C14/04 ,  C23C14/16 ,  H01L21/285

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.

摘要翻译： 我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻层的材料的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染。第一保护层 的材料通过传统的溅射或离子沉积溅射沉积在衬底表面上，结合足够低的衬底偏压，其中施加了该层的表面在保护层沉积期间不被腐蚀掉或被污染。 随后，使用离子沉积溅射在增加的衬底偏压下施加雕刻的第二材料层，以从材料的第一保护层的一部分和第二沉积材料层的一部分雕刻出形状。 该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层。

公开(公告)号：US20100255678A1

公开(公告)日：2010-10-07

申请号：US12802701

申请日：2010-06-11

申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： We disclose a method of depositing a metal seed layer on a wafer substrate comprising a plurality of recessed device features. The method comprises depositing a first portion of a copper seed layer on a wafer substrate without excessive build-up on the openings of each of the plurality of recessed device features, while obtaining bottom coverage without substantial sputtering of the bottom surface. The method also comprises depositing a second portion of the metal seed layer while redistributing at least a portion of the bottom coverage material to the sidewalls of each recessed device feature, to provide a uniform seed layer coverage over the interior surface of the recessed device features.

摘要翻译： 我们公开了在包括多个凹入的装置特征的晶片衬底上沉积金属种子层的方法。 该方法包括在晶片衬底上沉积铜晶种层的第一部分，而不会在多个凹陷元件特征中的每一个的开口上过多地累积，同时获得底部覆盖而无需基本上溅射底面。 该方法还包括沉积金属种子层的第二部分，同时将底部覆盖材料的至少一部分重新分配到每个凹陷装置特征的侧壁，以在凹陷装置特征的内表面上提供均匀的种子层覆盖。