METHOD FOR MANUFACTURING TRANSISTOR AND TRANSISTOR
    4.
    发明申请
    METHOD FOR MANUFACTURING TRANSISTOR AND TRANSISTOR 有权
    制造晶体管和晶体管的方法

    公开(公告)号:US20140183506A1

    公开(公告)日:2014-07-03

    申请号:US14178651

    申请日:2014-02-12

    CPC classification number: H01L51/0021 H01L51/0545 H01L51/0558 H01L51/105

    Abstract: A method for manufacturing a transistor includes: forming a base film for supporting a catalyst for electroless plating; forming a resist layer having an opening portion corresponding to source and drain electrodes onto the base film; causing the base film within the opening portion to support the catalyst for electroless plating and performing a first electroless plating; removing the resist layer; performing a second electroless plating on a surface of an electrode which is formed by the first electroless plating and forming the source and drain electrodes; and forming a semiconductor layer in contact with surfaces of the source and drain electrodes, the surfaces facing each other, wherein an energy level difference between a work function of a material which is used for the second electroless plating and an energy level of a molecular orbital which is used for electron transfer in a material of the semiconductor layer is less than an energy level difference between a work function of a material which is used for the first electroless plating and the energy level of the molecular orbital.

    Abstract translation: 一种制造晶体管的方法,包括:形成用于支撑化学镀的催化剂的基膜; 在所述基膜上形成具有对应于源电极和漏电极的开口部分的抗蚀剂层; 使所述开口部内的基膜支承无电镀用催化剂,进行第一无电镀; 去除抗蚀剂层; 在由所述第一无电镀形成的电极的表面上进行第二无电镀,形成所述源极和漏极; 以及形成与所述源极和漏极的表面接触的半导体层,所述表面彼此面对,其中用于所述第二无电镀的材料的功函数与分子轨道的能级之间的能级差 用于半导体层的材料中的电子转移的电子量小于用于第一化学镀的材料的功函数与分子轨道的能级之间的能级差。

    Fluidic device, fluid control method, testing device, testing method, and fluidic device manufacturing method

    公开(公告)号:US10677791B2

    公开(公告)日:2020-06-09

    申请号:US15386224

    申请日:2016-12-21

    Abstract: A fluidic device includes a valve configured to adjust a fluid flow in a first direction of a flow path. The fluidic device includes: a diaphragm of the valve; a first substrate having a groove that constitutes the flow path and a protrusion part at a position facing the diaphragm in the groove; and a second substrate to which the diaphragm is fixed at a first fixation part and a second fixation part, wherein a length from a first end part of the protrusion part to a second end part of the protrusion part seen in the first direction is greater than a length from the first fixation part to the second fixation part.

    Method for manufacturing transistor and transistor
    10.
    发明授权
    Method for manufacturing transistor and transistor 有权
    制造晶体管和晶体管的方法

    公开(公告)号:US09401478B2

    公开(公告)日:2016-07-26

    申请号:US14178651

    申请日:2014-02-12

    CPC classification number: H01L51/0021 H01L51/0545 H01L51/0558 H01L51/105

    Abstract: A method for manufacturing a transistor includes: forming a base film for supporting a catalyst for electroless plating; forming a resist layer having an opening portion corresponding to source and drain electrodes onto the base film; causing the base film within the opening portion to support the catalyst for electroless plating and performing a first electroless plating; removing the resist layer; performing a second electroless plating on a surface of an electrode which is formed by the first electroless plating and forming the source and drain electrodes; and forming a semiconductor layer in contact with surfaces of the source and drain electrodes, the surfaces facing each other, wherein an energy level difference between a work function of a material which is used for the second electroless plating and an energy level of a molecular orbital which is used for electron transfer in a material of the semiconductor layer is less than an energy level difference between a work function of a material which is used for the first electroless plating and the energy level of the molecular orbital.

    Abstract translation: 一种制造晶体管的方法,包括:形成用于支撑化学镀的催化剂的基膜; 在所述基膜上形成具有对应于源电极和漏电极的开口部分的抗蚀剂层; 使所述开口部内的基膜支承无电镀用催化剂,进行第一无电镀; 去除抗蚀剂层; 在由所述第一无电镀形成的电极的表面上进行第二无电镀,形成所述源极和漏极; 以及形成与所述源极和漏极的表面接触的半导体层,所述表面彼此面对,其中用于所述第二无电镀的材料的功函数与分子轨道的能级之间的能级差 用于半导体层的材料中的电子转移的电子量小于用于第一化学镀的材料的功函数与分子轨道的能级之间的能级差。

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