公开(公告)号：US20130119489A1

公开(公告)日：2013-05-16

申请号：US13294831

申请日：2011-11-11

申请人： Tallis Y. Chang ,  Yaoling Pan ,  John H. Hong ,  Chong U. Lee

发明人： Tallis Y. Chang ,  Yaoling Pan ,  John H. Hong ,  Chong U. Lee

IPC分类号： H01L31/18 ,  H01L31/0203

CPC分类号： B81C1/00293 ,  B81C2203/0145

摘要： A plurality of MEMS devices are formed on a substrate, a sacrificial layer is formed to cover each of the MEMS devices and a protective cap layer is formed on the sacrificial layer. A release hole is formed through the protective cap layer to the underlying sacrificial layer, and a releasing agent is introduced through the release hole to remove the sacrificial layer under the protective cap layer and expose a MEMS device. Optionally, the MEMS device can be released with the same releasing agent or, optionally, with a secondary releasing agent. The release hole is solder sealed, to form a hermetic seal of the MEMS device. Optionally, release holes are formed at a plurality of locations, each over a MEMS device and the releasing forms a plurality of hermetic sealed MEMS devices on the wafer substrate, which are singulated to form separate hermetically sealed MEMS devices.

摘要翻译： 在衬底上形成多个MEMS器件，形成牺牲层以覆盖每个MEMS器件，并且在牺牲层上形成保护帽层。 通过保护盖层形成释放孔到下面的牺牲层，并且通过释放孔引入脱模剂以除去保护盖层下面的牺牲层并暴露MEMS器件。 可选地，MEMS器件可以用相同的脱模剂或任选地与二次释放剂一起释放。 释放孔被焊接密封，以形成MEMS器件的气密密封。 可选地，在多个位置上形成释放孔，每个位置都在MEMS器件上，并且释放在晶片衬底上形成多个密封的MEMS器件，其被单个化以形成分开的密封的MEMS器件。

公开(公告)号：US20120242627A1

公开(公告)日：2012-09-27

申请号：US13052446

申请日：2011-03-21

申请人： Cheonhong Kim ,  John Hyunchul Hong ,  Yaoling Pan

发明人： Cheonhong Kim ,  John Hyunchul Hong ,  Yaoling Pan

IPC分类号： G06F3/038 ,  H01L29/24 ,  H01L29/04 ,  H01L21/385

CPC分类号： H01L29/66742 ,  G02B26/001 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78693

摘要： This disclosure provides systems, methods and apparatus for fabricating thin film transistor devices. In one aspect, a substrate having a source region, a drain region, and a channel region between the source region and the drain region is provided. The substrate also includes an oxide semiconductor layer, a first dielectric layer overlying the channel region, and a first metal layer on the dielectric layer. A second metal layer is formed on the oxide semiconductor layer overlying the source region and the drain region. The oxide semiconductor layer and the second metal layer are treated to form a heavily doped n-type oxide semiconductor in the oxide semiconductor layer overlying the source region and the drain region. An oxide in the second metal layer also can be formed.

摘要翻译： 本公开提供了用于制造薄膜晶体管器件的系统，方法和装置。 一方面，提供了在源极区域和漏极区域之间具有源极区域，漏极区域和沟道区域的衬底。 衬底还包括氧化物半导体层，覆盖沟道区的第一介电层和介电层上的第一金属层。 在覆盖源极区域和漏极区域的氧化物半导体层上形成第二金属层。 处理氧化物半导体层和第二金属层以在覆盖源极区和漏极区的氧化物半导体层中形成重掺杂的n型氧化物半导体。 也可以形成第二金属层中的氧化物。

公开(公告)号：US20100144103A1

公开(公告)日：2010-06-10

申请号：US12703043

申请日：2010-02-09

申请人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

发明人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

IPC分类号： H01L21/8232 ,  H01L21/302

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78681 ,  H01L29/7869 ,  Y10S977/762 ,  Y10S977/932 ,  Y10S977/938

摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.

摘要翻译： 描述了具有改进的门结构的电子设备的方法，系统和装置。 电子装置包括至少一个纳米线。 栅极接触沿至少一个纳米线的长度的至少一部分定位。 介电材料层在栅极接触和至少一个纳米线之间。 源极触点和漏极触点与至少一个纳米线接触。 源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。 另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。 环形第一栅极区域沿着纳米线长度的一部分包围纳米线。 第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。 源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

公开(公告)号：US20060255481A1

公开(公告)日：2006-11-16

申请号：US11490636

申请日：2006-07-21

申请人： Yaoling Pan ,  Xiangfeng Duan ,  Robert Dubrow ,  Jay Goldman ,  Shahriar Mostarshed ,  Chunming Niu ,  Linda Romano ,  Dave Stumbo

发明人： Yaoling Pan ,  Xiangfeng Duan ,  Robert Dubrow ,  Jay Goldman ,  Shahriar Mostarshed ,  Chunming Niu ,  Linda Romano ,  Dave Stumbo

IPC分类号： H01L21/20 ,  H01L21/31 ,  H01L21/00

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/162 ,  C01B32/18 ,  C30B11/12 ,  C30B25/00 ,  C30B29/06 ,  C30B29/60 ,  C30B29/605 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02521 ,  H01L21/02573 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02653 ,  H01L29/0665 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/7854 ,  H01L2924/0002 ,  Y10S438/962 ,  Y10S977/742 ,  Y10S977/743 ,  Y10S977/843 ,  Y10S977/891 ,  H01L2924/00

摘要： The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors. In a further aspect of the invention, methods to improve nanowire quality through the use of sacrifical growth layers are provided. In another aspect of the invention, methods for transferring nanowires from one substrate to another substrate are provided.

公开(公告)号：US20060214156A1

公开(公告)日：2006-09-28

申请号：US11233503

申请日：2005-09-22

申请人： Yaoling Pan ,  Francisco Leon ,  David Stumbo

发明人： Yaoling Pan ,  Francisco Leon ,  David Stumbo

IPC分类号： H01L29/08

CPC分类号： H01L51/0545 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0035 ,  H01L51/0037 ,  H01L51/0048 ,  H01L51/0049 ,  H01L51/0541 ,  H01L51/0566 ,  H01L51/4253 ,  H01L51/4266 ,  Y02E10/549 ,  Y02P70/521 ,  Y10S977/762 ,  Y10S977/763 ,  Y10S977/764

摘要： The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed. Several nanowire-TFT fabrication methods are also provided which in one exemplary embodiment includes providing a device substrate; depositing a first conductive polymer material layer on the device substrate; defining one or more gate contact regions in the conductive polymer layer; depositing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level; depositing a second conductive polymer material layer on the plurality of nanowires; and forming source and drain contact regions in the second conductive polymer material layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions.

摘要翻译： 本发明涉及使用并入和/或设置在导电聚合物层附近的纳米线（或诸如纳米带，纳米管等的其它纳米结构）的薄膜晶体管，以及用于生产这种晶体管的生产可扩展方法。 特别地，公开了包含导电聚合材料如聚苯胺（PANI）或聚吡咯（PPY）和一个或多个纳米线的复合材料，其中并入其中。 还提供了几种纳米线TFT制造方法，其在一个示例性实施例中包括提供器件衬底; 在器件衬底上沉积第一导电聚合物材料层; 限定所述导电聚合物层中的一个或多个栅极接触区域; 在所述导电聚合物层上以足够的纳米线密度沉积多个纳米线以实现工作电流水平; 在所述多个纳米线上沉积第二导电聚合物材料层; 以及在所述第二导电聚合物材料层中形成源极和漏极接触区域，从而提供与所述多个纳米线的电连接性，由此所述纳米线形成在所述源极和漏极区域中的相应长度之间具有长度的沟道。

公开(公告)号：US07091120B2

公开(公告)日：2006-08-15

申请号：US10910800

申请日：2004-08-04

申请人： Mihai Buretea ,  Jian Chen ,  Calvin Chow ,  Chunming Niu ,  Yaoling Pan ,  J. Wallace Parce ,  Linda T. Romano ,  David Stumbo

发明人： Mihai Buretea ,  Jian Chen ,  Calvin Chow ,  Chunming Niu ,  Yaoling Pan ,  J. Wallace Parce ,  Linda T. Romano ,  David Stumbo

IPC分类号： H01L21/28 ,  H01L21/3205

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78681 ,  H01L29/78696 ,  H01L33/06 ,  H01L33/24 ,  H01L51/0048 ,  H01L51/0545 ,  H01L2924/0002 ,  Y10T428/2913 ,  H01L2924/00

摘要： The present invention relates to a system and process for producing a nanowire-material composite. A substrate having nanowires attached to a portion of at least one surface is provided. A material is deposited over the portion to form the nanowire-material composite. The process further optionally includes separating the nanowire-material composite from the substrate to form a freestanding nanowire-material composite. The freestanding nanowire material composite is optionally further processed into an electronic substrate. A variety of electronic substrates can be produced using the methods described herein. For example, a multi-color light-emitting diode can be produced from multiple, stacked layers of nanowire-material composites, each composite layer emitting light at a different wavelength.

摘要翻译： 本发明涉及纳米线材料复合体的制造方法和制造方法。 提供了具有连接到至少一个表面的一部分的纳米线的衬底。 在该部分上沉积材料以形成纳米线材料复合材料。 该方法进一步可选地包括从衬底分离纳米线材料复合物以形成独立的纳米线材料复合材料。 独立的纳米线材料复合材料任选进一步加工成电子基片。 可以使用本文所述的方法来生产各种电子基板。 例如，多个发光二极管可以由多个层叠的纳米线材料复合体制成，每个复合层发射不同波长的光。

公开(公告)号：US20060081886A1

公开(公告)日：2006-04-20

申请号：US11233398

申请日：2005-09-22

申请人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda Romano

发明人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda Romano

IPC分类号： H01L29/76

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78681 ,  H01L29/7869 ,  Y10S977/762 ,  Y10S977/932 ,  Y10S977/938

摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.

摘要翻译： 描述了具有改进的门结构的电子设备的方法，系统和装置。 电子装置包括至少一个纳米线。 栅极接触沿至少一个纳米线的长度的至少一部分定位。 介电材料层在栅极接触和至少一个纳米线之间。 源极触点和漏极触点与至少一个纳米线接触。 源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。 另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。 环形第一栅极区域沿着纳米线长度的一部分包围纳米线。 第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。 源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

公开(公告)号：US20100323500A1

公开(公告)日：2010-12-23

申请号：US12854323

申请日：2010-08-11

申请人： Mihai Buretea ,  Jian Chen ,  Calvin Chow ,  Chunming Niu ,  Yaoling Pan ,  J. Wallace Parce ,  Linda T. Romano ,  David Stumbo

发明人： Mihai Buretea ,  Jian Chen ,  Calvin Chow ,  Chunming Niu ,  Yaoling Pan ,  J. Wallace Parce ,  Linda T. Romano ,  David Stumbo

IPC分类号： H01L21/20

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78681 ,  H01L29/78696 ,  H01L33/06 ,  H01L33/24 ,  H01L51/0048 ,  H01L51/0545 ,  H01L2924/0002 ,  Y10T428/2913 ,  H01L2924/00

摘要： The present invention relates to a system and process for producing a nanowire-material composite. A substrate having nanowires attached to a portion of at least one surface is provided. A material is deposited over the portion to form the nanowire-material composite. The process further optionally includes separating the nanowire-material composite from the substrate to form a freestanding nanowire-material composite. The freestanding nanowire material composite is optionally further processed into a electronic substrate. A variety of electronic substrates can be produced using the methods described herein. For example, a multi-color light-emitting diode can be produced from multiple, stacked layers of nanowire-material composites, each composite layer emitting light at a different wavelength.

摘要翻译： 本发明涉及纳米线材料复合体的制造方法和制造方法。 提供了具有连接到至少一个表面的一部分的纳米线的衬底。 在该部分上沉积材料以形成纳米线材料复合材料。 该方法进一步可选地包括从衬底分离纳米线材料复合物以形成独立的纳米线材料复合材料。 独立的纳米线材料复合材料任选进一步加工成电子基片。 可以使用本文所述的方法来生产各种电子基板。 例如，多个发光二极管可以由多个层叠的纳米线材料复合体制成，每个复合层发射不同波长的光。

公开(公告)号：US07667296B2

公开(公告)日：2010-02-23

申请号：US11525121

申请日：2006-09-22

申请人： David Stumbo ,  Jian Chen ,  David Heald ,  Yaoling Pan

发明人： David Stumbo ,  Jian Chen ,  David Heald ,  Yaoling Pan

IPC分类号： H01L29/93

CPC分类号： B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/93 ,  Y10S977/762

摘要： A nanowire capacitor and methods of making the same are disclosed. The nanowire capacitor includes a subrate and a semiconductor nanowire that is supported by the substrate. An insulator is formed on a portion of the surface of the nanowire. Additionally, an outer coaxial conductor is formed on a portion insulator and a contact coupled to the nanowire.

摘要翻译： 公开了一种纳米线电容器及其制造方法。 纳米线电容器包括由衬底和由衬底支撑的半导体纳米线。 绝缘体形成在纳米线表面的一部分上。 此外，外部同轴导体形成在部分绝缘体上和与纳米线耦合的触点。

公开(公告)号：US07569503B2

公开(公告)日：2009-08-04

申请号：US11271488

申请日：2005-11-10

申请人： Yaoling Pan ,  David P. Stumbo

发明人： Yaoling Pan ,  David P. Stumbo

IPC分类号： H01L21/00

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/7606 ,  H01L29/78696 ,  Y10S977/901 ,  Y10S977/963

摘要： Embodiments of the present invention are provided for improved contact doping and annealing systems and processes. In embodiments, a plasma ion immersion implantation (PIII) process is used for contact doping of nanowires and other nanoelement based thin film devices. According to further embodiments of the present invention, pulsed laser annealing using laser energy at relatively low laser fluences below about 100 mJ/cm2 (e.g., less than about 50 mJ/cm2, e.g., between about 2 and 18 mJ/cm2) is used to anneal nanowire and other nanoelement-based devices on substrates, such as low temperature flexible substrates, e.g., plastic substrates.

摘要翻译： 提供本发明的实施例用于改进的接触掺杂和退火系统和工艺。 在实施例中，等离子体离子浸没注入（PIII）工艺用于纳米线和其它基于纳米元件的薄膜器件的接触掺杂。 根据本发明的另外的实施例，使用使用低于约100mJ / cm 2（例如，小于约50mJ / cm 2，例如约2至18mJ / cm 2）的相对低的激​​光能量密度的激光能量的脉冲激光退火 以在基底上退火纳米线和其它基于纳米元件的器件，例如低温柔性衬底，例如塑料衬底。