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    AMORPHOUS OXIDE SEMICONDUCTOR THIN FILM TRANSISTOR FABRICATION METHOD
    1.
    发明申请
    AMORPHOUS OXIDE SEMICONDUCTOR THIN FILM TRANSISTOR FABRICATION METHOD 有权
    非晶氧化物半导体薄膜晶体管制造方法

    公开(公告)号：US20120242627A1

    公开(公告)日：2012-09-27

    申请号：US13052446

    申请日：2011-03-21

    申请人： Cheonhong Kim ,  John Hyunchul Hong ,  Yaoling Pan

    发明人： Cheonhong Kim ,  John Hyunchul Hong ,  Yaoling Pan

    IPC分类号： G06F3/038 ,  H01L29/24 ,  H01L29/04 ,  H01L21/385

    CPC分类号： H01L29/66742 ,  G02B26/001 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78693

    摘要： This disclosure provides systems, methods and apparatus for fabricating thin film transistor devices. In one aspect, a substrate having a source region, a drain region, and a channel region between the source region and the drain region is provided. The substrate also includes an oxide semiconductor layer, a first dielectric layer overlying the channel region, and a first metal layer on the dielectric layer. A second metal layer is formed on the oxide semiconductor layer overlying the source region and the drain region. The oxide semiconductor layer and the second metal layer are treated to form a heavily doped n-type oxide semiconductor in the oxide semiconductor layer overlying the source region and the drain region. An oxide in the second metal layer also can be formed.

    摘要翻译： 本公开提供了用于制造薄膜晶体管器件的系统，方法和装置。 一方面，提供了在源极区域和漏极区域之间具有源极区域，漏极区域和沟道区域的衬底。 衬底还包括氧化物半导体层，覆盖沟道区的第一介电层和介电层上的第一金属层。 在覆盖源极区域和漏极区域的氧化物半导体层上形成第二金属层。 处理氧化物半导体层和第二金属层以在覆盖源极区和漏极区的氧化物半导体层中形成重掺杂的n型氧化物半导体。 也可以形成第二金属层中的氧化物。

    Method, System and Apparatus for Gating Configurations and Improved Contacts in Nanowire-Based Electronic Devices
    2.
    发明申请
    Method, System and Apparatus for Gating Configurations and Improved Contacts in Nanowire-Based Electronic Devices 有权
    基于纳米线的电子设备中门控配置和改进接点的方法，系统和设备

    公开(公告)号：US20100144103A1

    公开(公告)日：2010-06-10

    申请号：US12703043

    申请日：2010-02-09

    申请人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

    发明人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

    IPC分类号： H01L21/8232 ,  H01L21/302

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78681 ,  H01L29/7869 ,  Y10S977/762 ,  Y10S977/932 ,  Y10S977/938

    摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.

    摘要翻译： 描述了具有改进的门结构的电子设备的方法，系统和装置。 电子装置包括至少一个纳米线。 栅极接触沿至少一个纳米线的长度的至少一部分定位。 介电材料层在栅极接触和至少一个纳米线之间。 源极触点和漏极触点与至少一个纳米线接触。 源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。 另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。 环形第一栅极区域沿着纳米线长度的一部分包围纳米线。 第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。 源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

    Fully integrated organic layered processes for making plastic electronics based on conductive polymers and semiconductor nanowires
    4.
    发明申请
    Fully integrated organic layered processes for making plastic electronics based on conductive polymers and semiconductor nanowires 失效
    用于制造基于导电聚合物和半导体纳米线的塑料电子器件的完全集成的有机分层工艺

    公开(公告)号：US20060214156A1

    公开(公告)日：2006-09-28

    申请号：US11233503

    申请日：2005-09-22

    申请人： Yaoling Pan ,  Francisco Leon ,  David Stumbo

    发明人： Yaoling Pan ,  Francisco Leon ,  David Stumbo

    IPC分类号： H01L29/08

    CPC分类号： H01L51/0545 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0035 ,  H01L51/0037 ,  H01L51/0048 ,  H01L51/0049 ,  H01L51/0541 ,  H01L51/0566 ,  H01L51/4253 ,  H01L51/4266 ,  Y02E10/549 ,  Y02P70/521 ,  Y10S977/762 ,  Y10S977/763 ,  Y10S977/764

    摘要： The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed. Several nanowire-TFT fabrication methods are also provided which in one exemplary embodiment includes providing a device substrate; depositing a first conductive polymer material layer on the device substrate; defining one or more gate contact regions in the conductive polymer layer; depositing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level; depositing a second conductive polymer material layer on the plurality of nanowires; and forming source and drain contact regions in the second conductive polymer material layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions.

    摘要翻译： 本发明涉及使用并入和/或设置在导电聚合物层附近的纳米线（或诸如纳米带，纳米管等的其它纳米结构）的薄膜晶体管，以及用于生产这种晶体管的生产可扩展方法。 特别地，公开了包含导电聚合材料如聚苯胺（PANI）或聚吡咯（PPY）和一个或多个纳米线的复合材料，其中并入其中。 还提供了几种纳米线TFT制造方法，其在一个示例性实施例中包括提供器件衬底; 在器件衬底上沉积第一导电聚合物材料层; 限定所述导电聚合物层中的一个或多个栅极接触区域; 在所述导电聚合物层上以足够的纳米线密度沉积多个纳米线以实现工作电流水平; 在所述多个纳米线上沉积第二导电聚合物材料层; 以及在所述第二导电聚合物材料层中形成源极和漏极接触区域，从而提供与所述多个纳米线的电连接性，由此所述纳米线形成在所述源极和漏极区域中的相应长度之间具有长度的沟道。

    Method, system and apparatus for gating configurations and improved contacts in nanowire-based electronic devices
    6.
    发明申请
    Method, system and apparatus for gating configurations and improved contacts in nanowire-based electronic devices 失效
    用于选通配置和改进基于纳米线的电子设备中的接触的方法，系统和设备

    公开(公告)号：US20060081886A1

    公开(公告)日：2006-04-20

    申请号：US11233398

    申请日：2005-09-22

    申请人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda Romano

    发明人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda Romano

    IPC分类号： H01L29/76

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78681 ,  H01L29/7869 ,  Y10S977/762 ,  Y10S977/932 ,  Y10S977/938

    摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.

    摘要翻译： 描述了具有改进的门结构的电子设备的方法，系统和装置。 电子装置包括至少一个纳米线。 栅极接触沿至少一个纳米线的长度的至少一部分定位。 介电材料层在栅极接触和至少一个纳米线之间。 源极触点和漏极触点与至少一个纳米线接触。 源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。 另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。 环形第一栅极区域沿着纳米线长度的一部分包围纳米线。 第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。 源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

    Contact doping and annealing systems and processes for nanowire thin films
    9.
    发明授权
    Contact doping and annealing systems and processes for nanowire thin films 失效
    接触纳米线薄膜的掺杂和退火系统和工艺

    公开(公告)号：US07569503B2

    公开(公告)日：2009-08-04

    申请号：US11271488

    申请日：2005-11-10

    申请人： Yaoling Pan ,  David P. Stumbo

    发明人： Yaoling Pan ,  David P. Stumbo

    IPC分类号： H01L21/00

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/7606 ,  H01L29/78696 ,  Y10S977/901 ,  Y10S977/963

    摘要： Embodiments of the present invention are provided for improved contact doping and annealing systems and processes. In embodiments, a plasma ion immersion implantation (PIII) process is used for contact doping of nanowires and other nanoelement based thin film devices. According to further embodiments of the present invention, pulsed laser annealing using laser energy at relatively low laser fluences below about 100 mJ/cm2 (e.g., less than about 50 mJ/cm2, e.g., between about 2 and 18 mJ/cm2) is used to anneal nanowire and other nanoelement-based devices on substrates, such as low temperature flexible substrates, e.g., plastic substrates.

    摘要翻译： 提供本发明的实施例用于改进的接触掺杂和退火系统和工艺。 在实施例中，等离子体离子浸没注入（PIII）工艺用于纳米线和其它基于纳米元件的薄膜器件的接触掺杂。 根据本发明的另外的实施例，使用使用低于约100mJ / cm 2（例如，小于约50mJ / cm 2，例如约2至18mJ / cm 2）的相对低的激​​光能量密度的激光能量的脉冲激光退火 以在基底上退火纳米线和其它基于纳米元件的器件，例如低温柔性衬底，例如塑料衬底。

    Method, System and Apparatus for Gating Configurations and Improved Contacts in Nanowire-Based Electronic Devices
    10.
    发明申请
    Method, System and Apparatus for Gating Configurations and Improved Contacts in Nanowire-Based Electronic Devices 失效
    基于纳米线的电子设备中门控配置和改进接点的方法，系统和设备

    公开(公告)号：US20090050974A1

    公开(公告)日：2009-02-26

    申请号：US12244573

    申请日：2008-10-02

    申请人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

    发明人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

    IPC分类号： H01L47/00 ,  H01L21/8234

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78681 ,  H01L29/7869 ,  Y10S977/762 ,  Y10S977/932 ,  Y10S977/938

    摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.

    摘要翻译： 描述了具有改进的门结构的电子设备的方法，系统和装置。 电子装置包括至少一个纳米线。 栅极接触沿至少一个纳米线的长度的至少一部分定位。 介电材料层在栅极接触和至少一个纳米线之间。 源极触点和漏极触点与至少一个纳米线接触。 源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。 另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。 环形第一栅极区域沿着纳米线长度的一部分包围纳米线。 第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。 源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。