公开(公告)号：US08901568B2

公开(公告)日：2014-12-02

申请号：US13381605

申请日：2011-02-07

Applicant: Takeyoshi Masuda ,  Keiji Wada ,  Misako Honaga

Inventor： Takeyoshi Masuda ,  Keiji Wada ,  Misako Honaga

IPC: H01L29/24 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7811 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/42372 ,  H01L29/66068

Abstract: A termination configuration of a silicon carbide insulating gate type semiconductor device includes a semiconductor layer of a first conductivity type having a first main face, a gate electrode, and a source interconnection, as well as a circumferential resurf region. The semiconductor layer includes a body region of a second conductivity type, a source region of the first conductivity type, a contact region of the second conductivity type, and a circumferential resurf region of the second conductivity type. A width of a portion of the circumferential resurf region excluding the body region is greater than or equal to ½ the thickness of at least the semiconductor layer. A silicon carbide insulating gate type semiconductor device of high breakdown voltage and high performance can be provided.

Abstract translation: 碳化硅绝缘栅型半导体器件的端接构造包括具有第一主面，栅电极和源极互连的第一导电类型的半导体层以及周向复原区域。 半导体层包括第二导电类型的主体区域，第一导电类型的源极区域，第二导电类型的接触区域和第二导电类型的周边复原区域。 除了身体区域之外的圆周清理区域的一部分的宽度大于或等于至少半导体层的厚度的1/2。 可以提供具有高击穿电压和高性能的碳化硅绝缘栅型半导体器件。

公开(公告)号：US08785301B2

公开(公告)日：2014-07-22

申请号：US13390869

申请日：2011-02-25

Applicant: Keiji Wada ,  Takeyoshi Masuda ,  Tomihito Miyazaki ,  Toru Hiyoshi ,  Satomi Itoh ,  Hiromu Shiomi

Inventor： Keiji Wada ,  Takeyoshi Masuda ,  Tomihito Miyazaki ,  Toru Hiyoshi ,  Satomi Itoh ,  Hiromu Shiomi

IPC: H01L21/322 ,  H01L21/31

CPC classification number: H01L21/02052 ,  H01L21/02057 ,  H01L21/67051 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7802

Abstract: A method of cleaning a SiC semiconductor includes the steps of forming an oxide film at the surface of a SiC semiconductor, and removing the oxide film. At the step of forming an oxide film, an oxide film is formed using ozone water having a concentration greater than or equal to 30 ppm. The forming step preferably includes the step of heating at least one of the surface of the SiC semiconductor and the ozone water. Thus, there can be obtained a method of cleaning a SiC semiconductor that can exhibit cleaning effect on the SiC semiconductor.

Abstract translation: 清洗SiC半导体的方法包括以下步骤：在SiC半导体的表面形成氧化膜，除去氧化物膜。 在形成氧化膜的步骤中，使用浓度大于或等于30ppm的臭氧水形成氧化膜。 成形步骤优选包括加热SiC半导体的表面和臭氧水中的至少一个的步骤。 因此，可以获得能够对SiC半导体具有清洁效果的SiC半导体的清洗方法。

公开(公告)号：US08697555B2

公开(公告)日：2014-04-15

申请号：US12526731

申请日：2008-08-21

Applicant: Kazuhiro Fujikawa ,  Shin Harada ,  Yasuo Namikawa ,  Takeyoshi Masuda

Inventor： Kazuhiro Fujikawa ,  Shin Harada ,  Yasuo Namikawa ,  Takeyoshi Masuda

IPC: H01L21/265

CPC classification number: H01L29/7802 ,  H01L21/046 ,  H01L21/67109 ,  H01L29/45 ,  H01L29/66068 ,  Y10T117/1068 ,  Y10T117/1088

Abstract: The invention offers a method of producing a semiconductor device that can suppress the worsening of the property due to surface roughening of a wafer by sufficiently suppressing the surface roughening of the wafer in the heat treatment step and a semiconductor device in which the worsening of the property caused by the surface roughening is suppressed. The method of producing a MOSFET as a semiconductor device is provided with a step of preparing a wafer 3 made of silicon carbide and an activation annealing step that performs activation annealing by heating the wafer 3. In the activation annealing step, the wafer 3 is heated in an atmosphere containing a vapor of silicon carbide generated from the SiC piece 61, which is a generating source other than the wafer 3.

Abstract translation: 本发明提供一种制造半导体器件的方法，该半导体器件能够通过在热处理步骤中充分抑制晶片的表面粗糙化以及其中性能恶化的半导体器件来抑制由于晶片的表面粗糙而导致的性能恶化 造成表面粗糙度受到抑制。 制造作为半导体器件的MOSFET的方法具有制备由碳化硅制成的晶片3的步骤和通过加热晶片3进行活化退火的活化退火步骤。在活化退火步骤中，晶片3被加热 在包含由除了晶片3之外的发生源的SiC片61产生的碳化硅蒸气的气氛中。

公开(公告)号：US08648349B2

公开(公告)日：2014-02-11

申请号：US13121122

申请日：2010-05-12

Applicant: Takeyoshi Masuda ,  Misako Honaga

Inventor： Takeyoshi Masuda ,  Misako Honaga

IPC: H01L29/15

CPC classification number: H01L29/7802 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66909 ,  H01L29/8083

Abstract: A MOSFET which is a semiconductor device capable of achieving a stable reverse breakdown voltage and reduced on-resistance includes a SiC wafer of an n conductivity type, a plurality of p bodies of a p conductivity type formed to include a first main surface of the SiC wafer, and n+ source regions of the n conductivity type formed in regions surrounded by the plurality of p bodies, respectively, when viewed two-dimensionally. Each of the p bodies has a circular shape when viewed two-dimensionally, and each of the n+ source regions is arranged concentrically with each of the p bodies and has a circular shape when viewed two-dimensionally. Each of the plurality of p bodies is arranged to be positioned at a vertex of a regular hexagon when viewed two-dimensionally.

Abstract translation: 作为能够实现稳定的反向击穿电压和降低的导通电阻的半导体器件的MOSFET包括n导电型的SiC晶片，形成为包括SiC晶片的第一主表面的多个p导电类型的多个p体 ，以及分别形成在由多个p体包围的区域中的n导电类型的n +源极区域。 每个p体在二维观察时具有圆形形状，并且n +源区域中的每一个与每个p体同心地布置，并且在二维观察时具有圆形形状。 当二维观察时，多个p体中的每一个被布置成定位在正六边形的顶点处。

公开(公告)号：US08564017B2

公开(公告)日：2013-10-22

申请号：US13485423

申请日：2012-05-31

Applicant: Misako Honaga ,  Takeyoshi Masuda ,  Keiji Wada ,  Toru Hiyoshi

Inventor： Misako Honaga ,  Takeyoshi Masuda ,  Keiji Wada ,  Toru Hiyoshi

IPC: H01L29/66 ,  H01L21/337 ,  H01L29/15

CPC classification number: H01L29/7802 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66068

Abstract: A drift layer has a thickness direction throughout which a current flows and has an impurity concentration N1d for a first conductivity type. A body region is provided on a portion of the drift layer, has a channel to be switched by a gate electrode, has an impurity concentration N1b for the first conductivity type, and has an impurity concentration N2b for the second conductivity type greater than the impurity concentration N1b. A JFET region is disposed adjacent to the body region on the drift layer, has an impurity concentration N1j for the first conductivity type, and has an impurity concentration N2j for the second conductivity type smaller than the impurity concentration N1j. N1j−N2j>N1d and N2j

Abstract translation: 漂移层具有电流流动的厚度方向，并具有用于第一导电类型的杂质浓度N1d。 身体区域设置在漂移层的一部分上，具有由栅电极切换的通道，具有用于第一导电类型的杂质浓度N1b，并且具有大于杂质的第二导电类型的杂质浓度N2b 浓度N1b。 JFET区域与漂移层上的体区附近配置，对于第一导电类型具有杂质浓度N1j，并且对于第二导电类型的杂质浓度N2j小于杂质浓度N1j。 N1j-N2j> N1d和N2j

公开(公告)号：US08513676B2

公开(公告)日：2013-08-20

申请号：US13512459

申请日：2010-12-17

Applicant: Shin Harada ,  Toru Hiyoshi ,  Keiji Wada ,  Takeyoshi Masuda

Inventor： Shin Harada ,  Toru Hiyoshi ,  Keiji Wada ,  Takeyoshi Masuda

IPC: H01L29/38

CPC classification number: H01L29/7802 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02609 ,  H01L21/049 ,  H01L21/2007 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/94

Abstract: A semiconductor device includes: a substrate made of silicon carbide and having a main surface having an off angle of not less than −3° and not more than +5° relative to a (0-33-8) plane in a direction; a p type layer made of silicon carbide and formed on the main surface of the substrate by means of epitaxial growth; and an oxide film formed in contact with a surface of the p type layer. A maximum value of nitrogen atom concentration is 1×1021 cm−3 or greater in a region within 10 nm from an interface between the p type layer and the oxide film.

Abstract translation: 一种半导体器件包括：由碳化硅制成的衬底，其具有相对于（0-33-8）面的偏离角不小于-3°且不大于+ 5°的主表面， 10方向; 由碳化硅制成的p型层，通过外延生长形成在衬底的主表面上; 以及形成为与p型层的表面接触的氧化物膜。 在p型层和氧化膜之间的界面10nm以内的区域中，氮原子浓度的最大值为1×1021cm-3以上。

公开(公告)号：US08513673B2

公开(公告)日：2013-08-20

申请号：US13120890

申请日：2010-03-23

Applicant: Keiji Wada ,  Shin Harada ,  Takeyoshi Masuda ,  Misako Honaga

Inventor： Keiji Wada ,  Shin Harada ,  Takeyoshi Masuda ,  Misako Honaga

IPC: H01L29/15 ,  H01L31/0312

CPC classification number: H01L29/045 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/78

Abstract: A MOSFET includes a silicon carbide (SiC) substrate having a main surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; a semiconductor layer formed on the main surface of the SiC substrate; and an insulating film formed in contact with a surface of the semiconductor layer. When the insulating film has a thickness of not less than 30 nm and not more than 46 nm, the threshold voltage thereof is not more than 2.3V. When the insulating film has a thickness of more than 46 nm and not more than 100 nm, the threshold voltage thereof is more than 2.3 V and not more than 4.9 V.

Abstract translation: MOSFET包括碳化硅（SiC）基板，其具有相对于{0001}面具有不小于50°且不大于65°的偏离角的主表面; 形成在所述SiC衬底的主表面上的半导体层; 以及与半导体层的表面接触形成的绝缘膜。 当绝缘膜的厚度不小于30nm且不大于46nm时，其阈值电压不大于2.3V。 当绝缘膜的厚度大于46nm且不大于100nm时，其阈值电压大于2.3V且不大于4.9V。

公开(公告)号：US20130017677A1

公开(公告)日：2013-01-17

申请号：US13546828

申请日：2012-07-11

Applicant: Taku Horii ,  Takeyoshi Masuda

Inventor： Taku Horii ,  Takeyoshi Masuda

IPC: H01L21/283

CPC classification number: H01L29/7802 ,  H01L21/0485 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068

Abstract: A method for manufacturing a MOSFET includes the steps of: forming a gate oxide film on an active layer, forming a gate electrode on the gate oxide film, forming a source contact electrode in ohmic contact with the active layer, and forming an interlayer insulating film made of silicon dioxide so as to cover the gate electrode after the source contact electrode is formed. The step of forming a source contact electrode includes the steps of forming a metal layer including aluminum so as to be in contact with the active layer, and alloying the metal layer.

Abstract translation: 一种制造MOSFET的方法包括以下步骤：在有源层上形成栅极氧化膜，在栅极氧化膜上形成栅电极，形成与有源层欧姆接触的源极接触电极，并形成层间绝缘膜 在形成源极接触电极之后，覆盖栅电极，由二氧化硅构成。 形成源极接触电极的步骤包括以下步骤：形成包含铝的金属层以与活性层接触，并使金属层合金化。

公开(公告)号：US20120313112A1

公开(公告)日：2012-12-13

申请号：US13490208

申请日：2012-06-06

Applicant: Keiji Wada ,  Takeyoshi Masuda ,  Misako Honaga ,  Toru Hiyoshi

Inventor： Keiji Wada ,  Takeyoshi Masuda ,  Misako Honaga ,  Toru Hiyoshi

IPC: H01L29/161

CPC classification number: H01L29/7802 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7813

Abstract: A MOSFET includes a silicon carbide substrate, a drift layer made of silicon carbide and including a main surface having an off angle of 50° or more and 65° or less with respect to a {0001} plane, and a gate oxide film formed on and in contact with the main surface of the drift layer. The drift layer includes a p type body region formed to include a region in contact with the gate oxide film. The p type body region has an impurity density of 5×1016 cm−3 or more. A plurality of p type regions of p conductivity type located apart from one another in a direction perpendicular to a thickness direction of the drift layer are arranged in a region in the drift layer lying between the p type body region and the silicon carbide substrate.

Abstract translation: MOSFET包括碳化硅衬底，由碳化硅制成的漂移层，并且包括相对于{0001}面具有50°以上且65°以下的偏离角的主表面，以及形成在 并与漂移层的主表面接触。 漂移层包括形成为包括与栅氧化膜接触的区域的p型体区。 p型体区的杂质浓度为5×10 16 cm -3以上。 在垂直于漂移层的厚度方向的方向上彼此分离的p导电类型的多个p型区域布置在位于p型体区域和碳化硅衬底之间的漂移层中的区域中。

公开(公告)号：US20120280255A1

公开(公告)日：2012-11-08

申请号：US13522216

申请日：2011-10-25

Applicant: Takeyoshi Masuda ,  Keiji Wada ,  Toru Hiyoshi

Inventor： Takeyoshi Masuda ,  Keiji Wada ,  Toru Hiyoshi

IPC: H01L29/16 ,  H01L21/336

CPC classification number: H01L29/66734 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/0465 ,  H01L21/049 ,  H01L29/0623 ,  H01L29/086 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7813

Abstract: An MOSFET includes a silicon carbide substrate, an active layer, a gate oxide film, and a gate electrode. The active layer includes a body region where an inversion layer is formed at a region in contact with the gate oxide film by application of voltage to the gate electrode. The body region includes a low concentration region arranged at a region where an inversion layer is formed, and containing impurities of low concentration, and a high concentration region adjacent to the low concentration region in the carrier mobile direction in the inversion layer, arranged in a region where the inversion layer is formed, and containing impurities higher in concentration than in the low concentration region.

Abstract translation: MOSFET包括碳化硅衬底，有源层，栅氧化物膜和栅电极。 有源层包括通过向栅电极施加电压而在与栅极氧化膜接触的区域处形成反型层的主体区域。 身体区域包括布置在反型层形成区域的低浓度区域，并且在反转层中包含低浓度杂质和与反转层中的载流子移动方向上的低浓度区域相邻的高浓度区域 形成反型层的区域，并且含有浓度高于低浓度区域的杂质。