公开(公告)号：US09899385B2

公开(公告)日：2018-02-20

申请号：US13480956

申请日：2012-05-25

申请人： Takashi Yamazaki ,  Shimpei Tsujikawa

发明人： Takashi Yamazaki ,  Shimpei Tsujikawa

IPC分类号： H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/02

CPC分类号： H01L27/0922 ,  H01L21/823842 ,  H01L27/0266 ,  H01L27/0285

摘要： A semiconductor integrated circuit includes a protected circuit connected to two power supply lines that provide a supply voltage, a detecting circuit that includes a resistive element and a capacitive element connected in series between two power supply lines and detects a surge generated in the power supply line based on potential variation of an inter-element connecting node, and a protection transistor that is connected between two power supply lines and has a control electrode connected to an output of the detecting circuit. The protection transistor has the control electrode formed from a different electrode material having a work function difference from a transistor of the same channel conductivity type in the protected circuit, to have a different threshold voltage from the transistor so that the amount of leakage current per unit channel width may be smaller compared with the transistor.

公开(公告)号：US20120307410A1

公开(公告)日：2012-12-06

申请号：US13480956

申请日：2012-05-25

申请人： Takashi Yamazaki ,  Shimpei Tsujikawa

发明人： Takashi Yamazaki ,  Shimpei Tsujikawa

IPC分类号： H02H3/02 ,  H01L21/336

CPC分类号： H01L27/0922 ,  H01L21/823842 ,  H01L27/0266 ,  H01L27/0285

摘要： A semiconductor integrated circuit includes a protected circuit connected to two power supply lines that provide a supply voltage, a detecting circuit that includes a resistive element and a capacitive element connected in series between two power supply lines and detects a surge generated in the power supply line based on potential variation of an inter-element connecting node, and a protection transistor that is connected between two power supply lines and has a control electrode connected to an output of the detecting circuit. The protection transistor has the control electrode formed from a different electrode material having a work function difference from a transistor of the same channel conductivity type in the protected circuit, to have a different threshold voltage from the transistor so that the amount of leakage current per unit channel width may be smaller compared with the transistor.

摘要翻译： 半导体集成电路包括连接到提供电源电压的两条电源线的保护电路，包括电阻元件和串联连接在两条电源线之间的电容元件的检测电路，并且检测在电源线中产生的浪涌 基于元件间连接节点的电位变化，以及连接在两个电源线之间并具有连接到检测电路的输出的控制电极的保护晶体管。 保护晶体管具有由与受保护电路中的相同沟道导电类型的晶体管具有功函数差的不同电极材料形成的控制电极，以具有与晶体管不同的阈值电压，使得每单位的漏电流量 通道宽度可能比晶体管更小。

公开(公告)号：US09065370B2

公开(公告)日：2015-06-23

申请号：US13395520

申请日：2010-09-14

申请人： Ryosuke Ito ,  Takanori Okubo ,  Tadaaki Chikashige ,  Takashi Yamazaki ,  Hikaru Matsumiya

发明人： Ryosuke Ito ,  Takanori Okubo ,  Tadaaki Chikashige ,  Takashi Yamazaki ,  Hikaru Matsumiya

IPC分类号： H02P9/04 ,  H02P9/30 ,  H02J3/38 ,  H02M7/219 ,  H02P3/22 ,  H02P101/15

CPC分类号： H02P9/305 ,  H02J3/386 ,  H02M7/219 ,  H02P3/22 ,  H02P2101/15 ,  Y02E10/723 ,  Y02E10/725 ,  Y02E10/763

摘要： Provided is a wind power generation apparatus to which general purpose inverters are applicable. An inverter in a constant-voltage mode is used. While a wind power generator is generating electricity, switching circuits are turned on and off at a controlled duty cycles to intermittently short-circuit an armature winding, boosting the voltage and controlling the rotational speed of a windmill rotating blade, with the result that the voltage applied to the inverter is made constant. At the activation, in order to prevent an excessive voltage from being generated while an inverter is changing from the stand-by state to the activated state, ON/OFF control of a switching circuit is performed to switch between the output voltage of a rectifier and the voltage generated at a resistor, with the result that the voltage is controlled and maintained at an appropriate value.

摘要翻译： 提供通用变频器适用的风力发电装置。 使用恒压模式的逆变器。 当风力发电机发电时，切换电路以受控的工作周期被接通和断开，以间歇地使电枢绕组短路，提升电压并控制风车旋转叶片的转速，结果电压 施加到逆变器上是恒定的。 在激活时，为了防止在逆变器从待机状态转变为激活状态时产生过大的电压，开关电路的ON / OFF控制被执行，以在整流器的输出电压和 在电阻器处产生的电压，结果是电压被控制并保持在适当的值。

公开(公告)号：US08988572B2

公开(公告)日：2015-03-24

申请号：US13237734

申请日：2011-09-20

申请人： Kanako Dowaki ,  Kazumasa Matsumoto ,  Hidehiko Saito ,  Takashi Yamazaki

发明人： Kanako Dowaki ,  Kazumasa Matsumoto ,  Hidehiko Saito ,  Takashi Yamazaki

IPC分类号： H04N5/335 ,  H04N5/217 ,  H04N5/3745 ,  H04N5/347 ,  H04N5/361

CPC分类号： H04N5/37457 ,  H04N5/347 ,  H04N5/361 ,  H04N5/37452

摘要： A radiation imaging apparatus includes: a radiation detection unit in which a plurality of photoelectric conversion units to convert radiation signals into charge signals and store the charge signals is located; a storage control unit configured to control the storage of the charge signals executed by the plurality of photoelectric conversion units; a reading control unit configured to control reading of the charge signals stored by the plurality of photoelectric conversion units; and a control unit configured to fix an indefinite potential generated at the radiation detection unit while at least one of the storage control of the charge signals by the storage control unit and the reading control of the charge signals by the reading control unit is not carried out.

摘要翻译： 辐射成像装置包括：放射线检测单元，其中定位将辐射信号转换成电荷信号并存储电荷信号的多个光电转换单元; 存储控制单元，被配置为控制由所述多个光电转换单元执行的所述电荷信号的存储; 读取控制单元，被配置为控制由所述多个光电转换单元存储的所述充电信号的读取; 以及控制单元，其被配置为固定在所述放射线检测单元处产生的不确定电位，同时由所述存储控制单元进行的所述充电信号的存储控制和所述读取控制单元的所述充电信号的读取控制中的至少一个不被执行 。

公开(公告)号：US08836836B2

公开(公告)日：2014-09-16

申请号：US13237362

申请日：2011-09-20

申请人： Takashi Yamazaki ,  Kazumasa Matsumoto ,  Hidehiko Saito ,  Kanako Dowaki

发明人： Takashi Yamazaki ,  Kazumasa Matsumoto ,  Hidehiko Saito ,  Kanako Dowaki

IPC分类号： H04N5/335 ,  H04N5/217 ,  H04N5/32 ,  H04N5/365 ,  H04N5/3745

CPC分类号： H04N5/32 ,  H04N5/365 ,  H04N5/37457

摘要： A radiation imaging apparatus includes an imaging unit and an imaging control unit. The imaging control unit causes a switch unit, an accumulation unit, a removal unit, a holding unit, and an addition unit, which constitute a pixel circuit of the imaging unit, to operate at a timing before an imaging operation by the imaging unit so as to fix unstable voltages of the accumulation unit, the removal unit, the holding unit, and the addition unit to a predetermined voltage of a power supply connected via a switch unit.

摘要翻译： 放射线摄像装置包括成像单元和成像控制单元。 成像控制单元使构成摄像单元的像素电路的开关单元，累积单元，去除单元，保持单元和加法单元在成像单元的成像操作之前的定时进行操作 将积存单元，去除单元，保持单元和加法单元的不稳定电压固定为经由开关单元连接的电源的预定电压。

公开(公告)号：US20140196505A1

公开(公告)日：2014-07-17

申请号：US14129673

申请日：2012-06-13

申请人： Tadashi Enomoto ,  Iwao Okazaki ,  Takashi Yamazaki ,  Masatoshi Hayakawa

发明人： Tadashi Enomoto ,  Iwao Okazaki ,  Takashi Yamazaki ,  Masatoshi Hayakawa

IPC分类号： C03B37/029

CPC分类号： C03B37/029 ,  C03B37/01257 ,  C03B2205/63 ,  F27B17/00 ,  H05B3/62 ,  H05B2203/025

摘要： The present invention provides a glass preform heating furnace in which the occurrence of arching is suppressed. The glass preform heating furnace is equipped with a susceptor (3); a slit heater (4); an insulator; and a furnace body, wherein, in the case that the space between the slit heater (4) and the susceptor or between the slit heater (4) and the conductive member closest to the slit heater is D, that the maximum value of the electric field in this space is E1, that the number of the slits in the slit heater is N, that the slit width of the slit heater is S, and that the maximum value of the electric field in the slit space is E2, the values of D, N and S are set so that E1≧E2 is established.

摘要翻译： 本发明提供一种玻璃预制件加热炉，其中抑制拱起的发生。 玻璃预制件加热炉配有基座（3）; 狭缝加热器（4）; 绝缘体 炉体，其中，狭缝加热器（4）与基座之间或狭缝加热器（4）与最靠近狭缝加热器的导电部件之间的间隔为D的情况下，电极的最大值 在该空间中的场为E1，狭缝加热器中的狭缝数为N，狭缝加热器的狭缝宽度为S，狭缝空间中的电场的最大值为E2， D，N，S被设定为使E1≥220成立。

公开(公告)号：US20120015687A1

公开(公告)日：2012-01-19

申请号：US13181737

申请日：2011-07-13

申请人： Keiju YAMADA ,  Takashi Yamazaki ,  Masatoshi Fukuda ,  Yasuhiro Koshio

发明人： Keiju YAMADA ,  Takashi Yamazaki ,  Masatoshi Fukuda ,  Yasuhiro Koshio

IPC分类号： H04W88/02 ,  H01L23/552

CPC分类号： H01L23/552 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： According to an embodiment, a semiconductor package includes a semiconductor chip mounted on an interposer board, a encapsulant sealing the semiconductor chip, and a conductive shielding layer covering the encapsulant and at least part of a side surface of the interposer board. The interposer board has plural vias through an insulating substrate. A part of the plural vias has a cutting plane exposing to the side surface of the interposer board and cut in a thickness direction of the interposer board. The cutting plane of the via is electrically connected to the conductive shielding layer.

摘要翻译： 根据实施例，半导体封装包括安装在插入板上的半导体芯片，密封半导体芯片的密封剂以及覆盖密封剂的导电屏蔽层和插入板的侧表面的至少一部分。 插入板具有通过绝缘基板的多个通路。 多个通孔的一部分具有暴露于插入板的侧表面并在插入板的厚度方向上切割的切割平面。 通孔的切割平面电连接到导电屏蔽层。

公开(公告)号：US07668760B2

公开(公告)日：2010-02-23

申请号：US09800524

申请日：2001-03-08

申请人： Kunimasa Suzuki ,  Yukari Takehira ,  Yasuhiro Ueda ,  Shigeaki Arai ,  Michiko Sekikawa ,  Lisa Naomi Schlais ,  Takashi Yamazaki ,  Tsuyoshi Maeda ,  Noriko Ishii ,  Kentaro Tanigaki ,  Hirokazu Takahashi ,  Futaba Shinohara

发明人： Kunimasa Suzuki ,  Yukari Takehira ,  Yasuhiro Ueda ,  Shigeaki Arai ,  Michiko Sekikawa ,  Lisa Naomi Schlais ,  Takashi Yamazaki ,  Tsuyoshi Maeda ,  Noriko Ishii ,  Kentaro Tanigaki ,  Hirokazu Takahashi ,  Futaba Shinohara

IPC分类号： G06Q10/00 ,  G06Q20/14 ,  G06G1/14

CPC分类号： G06Q10/087 ,  G06Q20/203

摘要： A distribution management device, a distribution management method, a program storage medium and a distribution management system are disclosed. The client order data of the merchandise 4 of the sales channel utilized the internet 3 and the store order data of the merchandise 4 for the quantity sold of the sales channels excluding the Internet 3 are received by the sales managing server 20 via the internet 3. The stock of merchandise 4 is controlled by the settlement/delivery instructing server 21 based on the client and store order data. The actual sales condition of merchandise in each sales channel is grasped by the shipment control server 55 based on the storage data and the delivery condition data obtained from the client and store order data and the storage data and delivery condition data obtained from the settlement/delivery instructing server 21, and the supply of merchandise 4 to the manufacturing factory will be instructed based on the actual sales condition. Thus, the distribution stocks to each of sales channels can be one-dimensionally controlled and can be efficiently distributed in the market based on the actual sales information. And thereby, the stocks can be constantly and certainly secured to various sales channels.

摘要翻译： 公开了一种分发管理装置，分发管理方法，程序存储介质和分发管理系统。 由销售管理服务器20经由因特网3接收销售渠道的商品4的客户订单数据，互联网3使用商品4的商店订单数据，而不包括因特网3的销售渠道销售的数量。 商品4的库存由结算/发货指示服务器21基于客户端和存储订单数据来控制。 基于从客户获得的存储数据和传送条件数据，存储订单数据以及从结算/传送获得的存储数据和传送条件数据，由出货控制服务器55掌握每个销售通道中的商品的实际销售状况 指示服务器21，并且将根据实际销售条件指示向制造工厂提供商品4。 因此，可以一维地控制各销售渠道的分销股，并且可以根据实际的销售信息有效地在市场上分配。 因此，股票可以不断地确定到各种销售渠道。

公开(公告)号：US07499340B2

公开(公告)日：2009-03-03

申请号：US12007336

申请日：2008-01-09

申请人： Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Manabu Tsunozaki ,  Kazuyoshi Oshima ,  Takashi Yamazaki ,  Yuji Sakai ,  Jiro Sawada ,  Yasunori Yamaguchi ,  Tetsurou Matsumoto ,  Shinji Udo ,  Hiroshi Yoshioka ,  Hirokazu Saito ,  Mitsuhiro Takano ,  Makoto Morino ,  Sinichi Miyatake ,  Eiji Miyamoto ,  Yasuhiro Kasama ,  Akira Endo ,  Ryoichi Hori ,  Jun Etoh ,  Masashi Horiguchi ,  Shinichi Ikenaga ,  Atsushi Kumata

发明人： Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Manabu Tsunozaki ,  Kazuyoshi Oshima ,  Takashi Yamazaki ,  Yuji Sakai ,  Jiro Sawada ,  Yasunori Yamaguchi ,  Tetsurou Matsumoto ,  Shinji Udo ,  Hiroshi Yoshioka ,  Hirokazu Saito ,  Mitsuhiro Takano ,  Makoto Morino ,  Sinichi Miyatake ,  Eiji Miyamoto ,  Yasuhiro Kasama ,  Akira Endo ,  Ryoichi Hori ,  Jun Etoh ,  Masashi Horiguchi ,  Shinichi Ikenaga ,  Atsushi Kumata

IPC分类号： G11C7/10

CPC分类号： H01L24/06 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C11/406 ,  G11C29/06 ,  G11C29/12005 ,  G11C29/12015 ,  G11C29/24 ,  G11C29/34 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/70 ,  G11C29/80 ,  G11C29/804 ,  G11C29/832 ,  G11C29/844 ,  G11C2029/2602 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11898 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01037 ,  H01L2924/01038 ,  H01L2924/01039 ,  H01L2924/01041 ,  H01L2924/01043 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01054 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/01084 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.

摘要翻译： 形成在半导体芯片上的半导体存储器件包括第一存储器阵列，多个第二存储器阵列，第一电压发生器和第一焊盘。 半导体芯片被分为第一，第二和第三矩形区域，第三矩形区域布置在第一矩形区域和第二矩形区域之间。 第一存储器阵列形成在第一矩形区域中。 第二存储器阵列形成在第二矩形区域中。 电压发生器和第一接合焊盘布置在第三矩形区域中。 第一接合焊盘布置在第一矩形区域和电压发生器之间，并且在电压发生器和第二存储器阵列之间没有布置接合焊盘。

公开(公告)号：US20080205111A1

公开(公告)日：2008-08-28

申请号：US12007336

申请日：2008-01-09

申请人： Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Manabu Tsunozaki ,  Kazuyoshi Oshima ,  Takashi Yamazaki ,  Yuji Sakai ,  Jiro Sawada ,  Yasunori Yamaguchi ,  Tetsurou Matsumoto ,  Shinji Udo ,  Hiroshi Yoshioka ,  Hirokazu Saito ,  Mitsuhiro Takano ,  Makoto Morino ,  Sinichi Miyatake ,  Eiji Miyamoto ,  Yasuhiro Kasama ,  Akira Endo ,  Ryoichi Hori ,  Jun Etoh ,  Masashi Horiguchi ,  Shinichi Ikenaga ,  Atsushi Kumata

发明人： Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Manabu Tsunozaki ,  Kazuyoshi Oshima ,  Takashi Yamazaki ,  Yuji Sakai ,  Jiro Sawada ,  Yasunori Yamaguchi ,  Tetsurou Matsumoto ,  Shinji Udo ,  Hiroshi Yoshioka ,  Hirokazu Saito ,  Mitsuhiro Takano ,  Makoto Morino ,  Sinichi Miyatake ,  Eiji Miyamoto ,  Yasuhiro Kasama ,  Akira Endo ,  Ryoichi Hori ,  Jun Etoh ,  Masashi Horiguchi ,  Shinichi Ikenaga ,  Atsushi Kumata

IPC分类号： G11C5/02 ,  G11C7/00

CPC分类号： H01L24/06 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C11/406 ,  G11C29/06 ,  G11C29/12005 ,  G11C29/12015 ,  G11C29/24 ,  G11C29/34 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/70 ,  G11C29/80 ,  G11C29/804 ,  G11C29/832 ,  G11C29/844 ,  G11C2029/2602 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11898 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01037 ,  H01L2924/01038 ,  H01L2924/01039 ,  H01L2924/01041 ,  H01L2924/01043 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01054 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/01084 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.

摘要翻译： 形成在半导体芯片上的半导体存储器件包括第一存储器阵列，多个第二存储器阵列，第一电压发生器和第一焊盘。 半导体芯片被分为第一，第二和第三矩形区域，第三矩形区域布置在第一矩形区域和第二矩形区域之间。 第一存储器阵列形成在第一矩形区域中。 第二存储器阵列形成在第二矩形区域中。 电压发生器和第一接合焊盘布置在第三矩形区域中。 第一接合焊盘布置在第一矩形区域和电压发生器之间，并且在电压发生器和第二存储器阵列之间没有布置接合焊盘。