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公开(公告)号：US20240357941A1
公开(公告)日：2024-10-24
申请号：US18763018
申请日：2024-07-03
Inventor： William J. Gallagher
CPC classification number: H10N50/01 , H01F41/34 , H01L21/0332 , H10B61/00 , H10N50/80 , H01F10/3254 , H01F10/329
Abstract: Some examples relate to an integrated circuit. The integrated circuit comprises a semiconductor substrate, a bottom electrode over the substrate, a circular magnetic tunneling junction (MTJ) disposed over an upper surface of bottom electrode, and a circular top electrode disposed over an upper surface of the magnetic tunneling junction. The circular top electrode is concentric to the circular magnetic tunneling junction, and a diameter of the circular magnetic tunneling junction is smaller than 60 nm or smaller than 30 nm.
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公开(公告)号：US12058940B2
公开(公告)日：2024-08-06
申请号：US17873315
申请日：2022-07-26
Inventor： William J. Gallagher
CPC classification number: H10N50/01 , H01F41/34 , H01L21/0332 , H10B61/00 , H10N50/80 , H01F10/3254 , H01F10/329
Abstract: Some examples relate to an integrated circuit. The integrated circuit comprises a semiconductor substrate, a bottom electrode over the substrate, a circular magnetic tunneling junction (MTJ) disposed over an upper surface of bottom electrode, and a circular top electrode disposed over an upper surface of the magnetic tunneling junction. The circular top electrode is concentric to the circular magnetic tunneling junction, and a diameter of the circular magnetic tunneling junction is smaller than 60 nm or smaller than 30 nm.
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公开(公告)号：US11864466B2
公开(公告)日：2024-01-02
申请号：US17385264
申请日：2021-07-26
Inventor： Shy-Jay Lin , Chwen Yu , William J. Gallagher
IPC: G11C11/16 , H01L43/08 , H01L43/12 , H01L43/02 , H10N50/01 , H01F10/32 , H01F41/34 , H10B61/00 , H10N50/10 , H10N50/80
CPC classification number: H10N50/01 , G11C11/161 , H01F10/3254 , H01F41/34 , H10B61/00 , H10B61/22 , H10N50/10 , H10N50/80
Abstract: In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode. The second insulating cover layer has an oxygen getter property.
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公开(公告)号：US20230076145A1
公开(公告)日：2023-03-09
申请号：US17982587
申请日：2022-11-08
Inventor： William J. Gallagher , Shy-Jay Lin , Ming Yuan Song
Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a memory cell overlying a substrate. A lower via underlies the memory cell. The lower via is laterally offset from the memory cell by a lateral distance. A first conductive layer is disposed vertically between the memory cell and the lower via and comprising a first material. The first conductive layer continuously extends along the lateral distance. A second conductive layer extends across an upper surface of the first conductive layer and comprises a second material different from the first material. A bottom surface of the second conductive layer is aligned with a bottom surface of the memory cell.
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Patent Agency Ranking
公开(公告)号：US20220359820A1
公开(公告)日：2022-11-10
申请号：US17873315
申请日：2022-07-26
Inventor： William J. Gallagher
IPC: H01L43/12 , H01L21/033 , H01L43/02 , H01F41/34 , H01L27/22
Abstract: Some examples relate to an integrated circuit. The integrated circuit comprises a semiconductor substrate, a bottom electrode over the substrate, a circular magnetic tunneling junction (MTJ) disposed over an upper surface of bottom electrode, and a circular top electrode disposed over an upper surface of the magnetic tunneling junction. The circular top electrode is concentric to the circular magnetic tunneling junction, and a diameter of the circular magnetic tunneling junction is smaller than 60 nm or smaller than 30 nm.
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公开(公告)号：US09767878B1
公开(公告)日：2017-09-19
申请号：US15174614
申请日：2016-06-06
Inventor： Yu-Der Chih , Tien-Wei Chiang , Chun-Jung Lin , Harry-Hak-Lay Chuang , William J. Gallagher
CPC classification number: G11C11/1675 , G11C11/16 , G11C11/161 , G11C11/1673
Abstract: A method for controlling a magnetic memory device is provided. The method includes: applying a first control signal and a second control signal to a ferromagnetic fixed layer and a ferromagnetic free layer of the magnetic memory device respectively, wherein a first voltage level of the first control signal is lower than a second voltage level of the second control signal; sensing a first current signal flowing through the magnetic memory device; and determining a logical state of a first data bit according to the first current signal.
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公开(公告)号：US11778924B2
公开(公告)日：2023-10-03
申请号：US17885328
申请日：2022-08-10
Inventor： MingYuan Song , Shy-Jay Lin , William J. Gallagher , Hiroki Noguchi
CPC classification number: H10N50/80 , G11C11/1655 , G11C11/1657 , H10N50/01 , H10N50/85
Abstract: A magnetic memory device includes a magnetic tunnel junction (MTJ) stack, a spin-orbit torque (SOT) induction wiring disposed over the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, and a selector layer coupled to the first terminal.
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公开(公告)号：US12041855B2
公开(公告)日：2024-07-16
申请号：US18227867
申请日：2023-07-28
Inventor： MingYuan Song , Shy-Jay Lin , William J. Gallagher , Hiroki Noguchi
CPC classification number: H10N50/80 , G11C11/1655 , G11C11/1657 , H10N50/01 , H10N50/85
Abstract: A magnetic memory device includes a magnetic tunnel junction (MTJ) stack, a spin-orbit torque (SOT) induction wiring disposed over the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, and a selector layer coupled to the first terminal.
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公开(公告)号：US20240090237A1
公开(公告)日：2024-03-14
申请号：US18513968
申请日：2023-11-20
Inventor： William J. Gallagher , Shy-Jay Lin , Ming Yuan Song
Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a memory cell overlying a substrate. A lower via underlies the memory cell. The lower via is laterally offset from the memory cell by a lateral distance. A first conductive layer is disposed vertically between the memory cell and the lower via and comprising a first material. The first conductive layer continuously extends along the lateral distance. A second conductive layer extends across an upper surface of the first conductive layer and comprises a second material different from the first material. A bottom surface of the second conductive layer is aligned with a bottom surface of the memory cell.
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