-
公开(公告)号：US10734227B2
公开(公告)日：2020-08-04
申请号：US16430114
申请日：2019-06-03
发明人： Dong-Sheng Li , Chia-Hui Lin , Kai Hung Cheng , Yao-Hsu Sun , Wen-Cheng Wu , Bo-Cyuan Lu , Sung-En Lin , Tai-Chun Huang
IPC分类号： H01L21/027 , H01L21/033 , H01L21/02 , H01L21/28 , H01L21/3213 , H01L21/311 , H01L21/8238 , G03F7/09 , G03F7/16 , G03F7/20 , G03F7/26
摘要： A four-layer photoresist and method of forming the same are disclosed. In an embodiment, a method includes forming a semiconductor fin; depositing a target layer on the semiconductor fin; depositing a BARC layer on the target layer; depositing a first mask layer over the BARC layer, the first mask layer being deposited using a plasma process with an RF power of less than 50 W; depositing a second mask layer over the first mask layer using a plasma process with an RF power of less than 500 W; depositing a photoresist layer over the second mask layer; patterning the photoresist layer, the second mask layer, the first mask layer, and the BARC layer to form a first mask; and selectively removing the target layer from a first portion of the semiconductor fin using the first mask, the target layer remaining on a second portion of the semiconductor fin.
-
公开(公告)号：US10522541B2
公开(公告)日：2019-12-31
申请号：US16390398
申请日：2019-04-22
发明人： Shih-Wen Huang , Chia-Hui Lin , Shin-Yeu Tsai , Kai Hung Cheng
IPC分类号： H01L21/762 , H01L27/088 , H01L29/06 , H01L21/8234 , H01L21/306 , H01L21/324 , H01L21/225
摘要： A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.
-
公开(公告)号：US09881918B1
公开(公告)日：2018-01-30
申请号：US15281568
申请日：2016-09-30
发明人： Shih-Wen Huang , Chia-Hui Lin , Shin-Yeu Tsai , Kai Hung Cheng
IPC分类号： H01L21/324 , H01L27/088 , H01L29/06 , H01L21/762 , H01L21/8234 , H01L21/306 , H01L21/225
CPC分类号： H01L27/0886 , H01L21/2254 , H01L21/30604 , H01L21/324 , H01L21/76237 , H01L21/823431 , H01L21/823481 , H01L29/0649
摘要： A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.
-
公开(公告)号：US10269796B2
公开(公告)日：2019-04-23
申请号：US15867255
申请日：2018-01-10
发明人： Shih-Wen Huang , Chia-Hui Lin , Shin-Yeu Tsai , Kai Hung Cheng
IPC分类号： H01L27/088 , H01L29/06 , H01L21/762 , H01L21/8234 , H01L21/306 , H01L21/324 , H01L21/225
摘要： A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.
-
公开(公告)号：US11600530B2
公开(公告)日：2023-03-07
申请号：US16213140
申请日：2018-12-07
发明人： Chun-Yi Lee , Hong-Hsien Ke , Chung-Ting Ko , Chia-Hui Lin , Jr-Hung Li
IPC分类号： H01L21/8234 , H01L21/02 , H01L21/311 , C23C16/34 , C23C16/455
摘要： An etch stop layer is formed over a semiconductor fin and gate stack. The etch stop layer is formed utilizing a series of pulses of precursor materials. A first pulse introduces a first precursor material to the semiconductor fin and gate stack. A second pulse introduces a second precursor material, which is turned into a plasma and then directed towards the semiconductor fin and gate stack in an anisotropic deposition process. As such, a thickness of the etch stop layer along a bottom surface is larger than a thickness of the etch stop layer along sidewalls.
-
公开(公告)号：US20200043799A1
公开(公告)日：2020-02-06
申请号：US16213140
申请日：2018-12-07
发明人： Chun-Yi Lee , Hong-Hsien Ke , Chung-Ting Ko , Chia-Hui Lin , Jr-Hung Li
IPC分类号： H01L21/8234 , H01L21/02 , H01L21/311
摘要： An etch stop layer is formed over a semiconductor fin and gate stack. The etch stop layer is formed utilizing a series of pulses of precursor materials. A first pulse introduces a first precursor material to the semiconductor fin and gate stack. A second pulse introduces a second precursor material, which is turned into a plasma and then directed towards the semiconductor fin and gate stack in an anisotropic deposition process. As such, a thickness of the etch stop layer along a bottom surface is larger than a thickness of the etch stop layer along sidewalls.
-
公开(公告)号：US20180130800A1
公开(公告)日：2018-05-10
申请号：US15867255
申请日：2018-01-10
发明人： Shih-Wen Huang , Chia-Hui Lin , Shin-Yeu Tsai , Kai Hung Cheng
IPC分类号： H01L27/088 , H01L21/225 , H01L21/324 , H01L21/8234 , H01L21/762 , H01L29/06 , H01L21/306
CPC分类号： H01L27/0886 , H01L21/2254 , H01L21/30604 , H01L21/324 , H01L21/76237 , H01L21/823431 , H01L21/823481 , H01L29/0649
摘要： A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.
-
公开(公告)号：US20230352418A1
公开(公告)日：2023-11-02
申请号：US17730217
申请日：2022-04-27
发明人： Yu-Hung Lin , Po-Hsun Chang , Yu-Kuang Liao , Chia-Hui Lin , Shih-Peng Tai , Kuo-Chung Yee
IPC分类号： H01L23/538 , H01L21/48 , H01L23/00
CPC分类号： H01L23/5389 , H01L23/5383 , H01L23/5386 , H01L21/4853 , H01L21/4857 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/20 , H01L24/80 , H01L2224/03614 , H01L2224/05018 , H01L2224/0508 , H01L2224/08145 , H01L2224/214 , H01L2224/80895 , H01L2224/80896
摘要： A semiconductor die, a semiconductor package and manufacturing methods thereof are provided. The semiconductor die includes: a front-end-of-line (FEOL) structure, built on a semiconductor substrate; a back-end-of-line (BEOL) structure, formed on the FEOL structure, and including a stack of metallization layers; and bonding metals, disposed on the BEOL structure. The bonding metals include: a conductive pad, disposed over the BEOL structure, and electrically connected to the metallization layers in the BEOL structure; a conductive capping layer, lining along a top surface of the conductive pad; and an engaging feature, landing on the conductive capping layer and separated from the conductive pad by the conductive capping layer. The semiconductor die is bonded to another semiconductor die or a package component by the engaging feature.
-
公开(公告)号：US20190252379A1
公开(公告)日：2019-08-15
申请号：US16390398
申请日：2019-04-22
发明人： Shih-Wen Huang , Chia-Hui Lin , Shin-Yeu Tsai , Kai Hung Cheng
IPC分类号： H01L27/088 , H01L21/225 , H01L21/324 , H01L21/8234 , H01L29/06 , H01L21/762 , H01L21/306
摘要： A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.
-
公开(公告)号：US12087834B2
公开(公告)日：2024-09-10
申请号：US17686978
申请日：2022-03-04
发明人： Shih-Wen Huang , Chung-Ting Ko , Hong-Hsien Ke , Chia-Hui Lin , Tai-Chun Huang
IPC分类号： H01L29/417 , H01L21/02 , H01L21/311 , H01L21/3115 , H01L21/768 , H01L21/8234 , H01L29/08 , H01L29/45 , H01L29/66 , H01L29/78
CPC分类号： H01L29/41791 , H01L21/02063 , H01L21/0217 , H01L21/02321 , H01L21/0234 , H01L21/02343 , H01L21/31111 , H01L21/31116 , H01L21/3115 , H01L21/76802 , H01L21/76831 , H01L21/76877 , H01L21/823431 , H01L21/823475 , H01L29/0847 , H01L29/41766 , H01L29/45 , H01L29/66795 , H01L29/7851 , H01L29/665 , H01L29/66545 , H01L29/7848
摘要： A semiconductor structure is provided. The semiconductor structure includes a gate structure, a source/drain structure, a barrier layer, and a glue layer. The gate structure is over a fin structure. The source/drain structure is in the fin structure and adjacent to the gate structure. The barrier layer is over the source/drain structure. The glue layer is adjacent to the barrier layer. The glue layer has an extending portion in direct contact with the gate structure.
-
-
-
-
-
-
-
-
-
搜索结果
13 条记录 (耗时 0.021 秒)
