公开(公告)号：US20150270153A1

公开(公告)日：2015-09-24

申请号：US14733352

申请日：2015-06-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： I-Ming Chang ,  Wen-Huei Guo ,  Chih-Hao Chang ,  Shou-Zen Chang ,  Clement Hsingjen Wann ,  Tung Ying Lee ,  Cheng-Long Chen ,  Jui-Chien Huang

IPC分类号： H01L21/687 ,  H01L21/683

CPC分类号： H01L21/687 ,  H01L21/6838 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/7845 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/785

摘要： An apparatus for and a method of forming a semiconductor structure is provided. The apparatus includes a substrate holder that maintains a substrate such that the processing surface is curved, such as a convex or a concave shape. The substrate is held in place using point contacts, a plurality of continuous contacts extending partially around the substrate, and/or a continuous ring extending completely around the substrate. The processing may include, for example, forming source/drain regions, channel regions, silicides, stress memorization layers, or the like.

摘要翻译： 提供了一种形成半导体结构的装置和方法。 该装置包括：基板保持件，其保持基板，使得处理表面是弯曲的，例如凸形或凹形。 基板使用点接触保持就位，多个连续接触部分围绕基板延伸，和/或完全围绕基板延伸的连续环。 处理可以包括例如形成源极/漏极区域，沟道区域，硅化物，应力存储层等。

公开(公告)号：US10700176B2

公开(公告)日：2020-06-30

申请号：US16663014

申请日：2019-10-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Hao Chang ,  Ming-Shan Shieh ,  Cheng-Long Chen ,  Chin-Chi Wang ,  Chi-Wen Liu ,  Wai-Yi Lien ,  Chih-Hao Wang

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/04 ,  H01L29/417 ,  H01L29/775

摘要： Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.

公开(公告)号：US09899489B2

公开(公告)日：2018-02-20

申请号：US14660542

申请日：2015-03-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Hao Chang ,  Ming-Shan Shieh ,  Cheng-Long Chen ,  Chin-Chi Wang ,  Chi-Wen Liu ,  Wai-Yi Lien ,  Chih-Hao Wang

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/283 ,  H01L21/02

CPC分类号： H01L29/42392 ,  B82Y10/00 ,  H01L21/823807 ,  H01L21/823885 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/66439 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827

摘要： Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.

公开(公告)号：US09978630B2

公开(公告)日：2018-05-22

申请号：US14733352

申请日：2015-06-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： I-Ming Chang ,  Wen-Huei Guo ,  Chih-Hao Chang ,  Shou-Zen Chang ,  Clement Hsingjen Wann ,  Tung Ying Lee ,  Cheng-Long Chen ,  Jui-Chien Huang

IPC分类号： H01L21/687 ,  H01L29/78 ,  H01L29/10 ,  H01L21/683 ,  H01L29/66

CPC分类号： H01L21/687 ,  H01L21/6838 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/7845 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/785

摘要： An apparatus for and a method of forming a semiconductor structure is provided. The apparatus includes a substrate holder that maintains a substrate such that the processing surface is curved, such as a convex or a concave shape. The substrate is held in place using point contacts, a plurality of continuous contacts extending partially around the substrate, and/or a continuous ring extending completely around the substrate. The processing may include, for example, forming source/drain regions, channel regions, silicides, stress memorization layers, or the like.

公开(公告)号：US20160133746A1

公开(公告)日：2016-05-12

申请号：US14536119

申请日：2014-11-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Huan-Chieh Su ,  Cheng-Long Chen ,  Ching-Hong Jiang ,  Clement Hsingjen Wann

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/321 ,  H01L29/66

CPC分类号： H01L29/66795 ,  H01L21/76229 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/1054

摘要： An embodiment method includes forming a first fin and a second fin over a semiconductor substrate. The first fin includes a first semiconductor strip of a first type, and the second fin includes a second semiconductor strip of the first type. The method further includes replacing the second semiconductor strip with a third semiconductor strip of a second type different than the first type. Replacing the second semiconductor strip includes masking the first fin using a barrier layer while replacing the second semiconductor strip and performing a chemical mechanical polish (CMP) on the third semiconductor strip using a slurry that planarizes the third semiconductor strip at a faster rate than the barrier layer. In some embodiments, the method may further include depositing a sacrificial layer over a wafer containing the first and second fins and performing a non-selective CMP to substantially level a top surface of the wafer.

摘要翻译： 一种实施方式包括在半导体衬底上形成第一鳍片和第二鳍片。 第一鳍包括第一类型的第一半导体条，第二鳍包括第一类型的第二半导体条。 该方法还包括用不同于第一类型的第二类型的第三半导体条替换第二半导体条。 更换第二半导体条包括使用阻挡层掩蔽第一鳍片，同时替换第二半导体条并在第三半导体条上执行化学机械抛光（CMP），该浆料使第三半导体条带以比屏障更快的速率平坦化 层。 在一些实施例中，该方法还可以包括在包含第一和第二鳍片的晶片之上沉积牺牲层，并且执行非选择性CMP以使晶片的顶表面基本上水平。

公开(公告)号：US10483367B2

公开(公告)日：2019-11-19

申请号：US15872361

申请日：2018-01-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Hao Chang ,  Ming-Shan Shieh ,  Cheng-Long Chen ,  Chin-Chi Wang ,  Chi-Wen Liu ,  Wai-Yi Lien ,  Chih-Hao Wang

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/283 ,  H01L21/02 ,  B82Y10/00 ,  H01L29/417 ,  H01L29/775 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08

摘要： Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.

公开(公告)号：US20180138282A1

公开(公告)日：2018-05-17

申请号：US15872361

申请日：2018-01-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Hao Chang ,  Ming-Shan Shieh ,  Cheng-Long Chen ,  Chin-Chi Wang ,  Chi-Wen Liu ,  Wai-Yi Lien ,  Chih-Hao Wang

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

CPC分类号： H01L29/42392 ,  B82Y10/00 ,  H01L21/823807 ,  H01L21/823885 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/66439 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827

摘要： Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.

公开(公告)号：US20160240623A1

公开(公告)日：2016-08-18

申请号：US14621628

申请日：2015-02-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Hao Chang ,  Ming-Shan Shieh ,  Cheng-Long Chen ,  Chin-Chi Wang ,  Chi-Wen Liu ,  Wai-Yi Lien ,  Chih-Hao Wang

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78 ,  H01L29/40

CPC分类号： H01L29/0676 ,  B82Y10/00 ,  H01L21/823814 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827

摘要： Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.

摘要翻译： 描述了垂直门（VGAA）装置及其制造方法。 一种用于制造VGAA器件的方法包括：暴露从掺杂区域延伸的突起的第一部分的顶表面和侧壁，其中突起的第二部分被栅极堆叠包围; 并且使用外延生长工艺来扩大突起的第一部分。

公开(公告)号：US20200075742A1

公开(公告)日：2020-03-05

申请号：US16663014

申请日：2019-10-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Hao Chang ,  Ming-Shan Shieh ,  Cheng-Long Chen ,  Chin-Chi Wang ,  Chi-Wen Liu ,  Wai-Yi Lien ,  Chih-Hao Wang

IPC分类号： H01L29/423 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/775 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/04 ,  H01L29/417 ,  H01L29/08

摘要： Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.

公开(公告)号：US09543417B2

公开(公告)日：2017-01-10

申请号：US14536119

申请日：2014-11-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Huan-Chieh Su ,  Cheng-Long Chen ,  Ching-Hong Jiang ,  Clement Hsingjen Wann

IPC分类号： H01L21/8234 ,  H01L29/66

CPC分类号： H01L29/66795 ,  H01L21/76229 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/1054

摘要： An embodiment method includes forming a first fin and a second fin over a semiconductor substrate. The first fin includes a first semiconductor strip of a first type, and the second fin includes a second semiconductor strip of the first type. The method further includes replacing the second semiconductor strip with a third semiconductor strip of a second type different than the first type. Replacing the second semiconductor strip includes masking the first fin using a barrier layer while replacing the second semiconductor strip and performing a chemical mechanical polish (CMP) on the third semiconductor strip using a slurry that planarizes the third semiconductor strip at a faster rate than the barrier layer. In some embodiments, the method may further include depositing a sacrificial layer over a wafer containing the first and second fins and performing a non-selective CMP to substantially level a top surface of the wafer.

摘要翻译： 一种实施方式包括在半导体衬底上形成第一鳍片和第二鳍片。 第一鳍包括第一类型的第一半导体条，第二鳍包括第一类型的第二半导体条。 该方法还包括用不同于第一类型的第二类型的第三半导体条替换第二半导体条。 更换第二半导体条包括使用阻挡层掩蔽第一鳍片，同时替换第二半导体条并在第三半导体条上执行化学机械抛光（CMP），该浆料使第三半导体条带以比屏障更快的速率平坦化 层。 在一些实施例中，该方法还可以包括在包含第一和第二鳍片的晶片之上沉积牺牲层，并且执行非选择性CMP以使晶片的顶表面基本上水平。