公开(公告)号：US20230387001A1

公开(公告)日：2023-11-30

申请号：US18447664

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo LIAO ,  Wei Ju Lee ,  Cheng-Ting Chung ,  Hou-Yu Chen ,  Chun-Fu Cheng ,  Kuan-Lun Cheng

IPC: H01L23/522 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L23/5226 ,  H01L29/66795 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/785

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.

公开(公告)号：US20230039440A1

公开(公告)日：2023-02-09

申请号：US17695605

申请日：2022-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Huan JAO ,  Huan-Chieh SU ,  Yi-Bo LIAO ,  Cheng-Chi CHUANG ,  Jin CAI ,  Chih-Hao WANG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/45 ,  H01L29/417 ,  H01L29/40

Abstract: A device includes a substrate. A channel region of a transistor overlies the substrate and a source/drain region is in contact with the channel region. The source/drain region is adjacent to the channel region along a first direction. A source/drain contact is disposed on the source/drain region. A gate electrode is disposed on the channel region and a gate contact is disposed on the gate electrode. A first low-k dielectric layer is disposed between the gate contact and the source/drain contact along the first direction.

公开(公告)号：US20230307456A1

公开(公告)日：2023-09-28

申请号：US17888261

申请日：2022-08-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Yu LIN ,  Yi-Han WANG ,  Chun-Fu CHENG ,  Cheng-Yin WANG ,  Yi-Bo LIAO ,  Szuya LIAO

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/0847 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/66439 ,  H01L21/823807 ,  H01L21/823814

Abstract: An integrated circuit includes a complimentary field effect transistor (CFET). The CFET includes a first transistor having a first semiconductor nanostructure corresponding to a channel region of the first semiconductor nanostructure and a first gate metal surrounding the second semiconductor nanostructure. The CFET includes a transistor including a second semiconductor nanostructure above the first semiconductor nanostructure and a second gate metal surrounding the second semiconductor nanostructure. The CFET includes an isolation structure between the first and second semiconductor nanostructures.

公开(公告)号：US20240120273A1

公开(公告)日：2024-04-11

申请号：US18172246

申请日：2023-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo LIAO ,  Jin CAI

IPC: H01L23/522 ,  H10B10/00

CPC classification number: H01L23/5226 ,  H10B10/125

Abstract: A device includes: a first stack of first semiconductor nanostructures; a second stack of second semiconductor nanostructures on the first stack of semiconductor nanostructures; a third stack of first semiconductor nanostructures adjacent the first stack; a first gate structure wrapping around the first stack and the second stack; a second gate structure wrapping around the third stack; a gate isolation structure between the first gate structure and the second gate structure; a dielectric layer on the second gate structure and laterally abutting the gate isolation structure; and a via. The via includes: a first portion that extends in a first direction, the first portion being on the first gate structure, the gate isolation structure and the dielectric layer; and a second portion that extends in a second direction transverse the first direction.

公开(公告)号：US20230052295A1

公开(公告)日：2023-02-16

申请号：US17580532

申请日：2022-01-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo LIAO ,  Yu-Xuan HUANG ,  Cheng-Ting CHUNG ,  Hou-Yu CHEN

IPC: H01L29/06 ,  H01L29/66

Abstract: A device includes a substrate, a gate structure, a capping layer, a source/drain region, a source/drain contact, and an air spacer. The gate structure wraps around at least one vertical stack of nanostructure channels over the substrate. The capping layer is on the gate structure. The source/drain region abuts the gate structure. The source/drain contact is on the source/drain region. The air spacer is between the capping layer and the source/drain contact.

公开(公告)号：US20210134718A1

公开(公告)日：2021-05-06

申请号：US16832833

申请日：2020-03-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo LIAO ,  Wei Ju Lee ,  Cheng-Ting Chung ,  Hou-Yu Chen ,  Chun-Fu Cheng ,  Kuan-Lun Cheng

IPC: H01L23/522 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L23/528

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.