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    DESIGN RULE CHECKING FOR CONFINING WAVEFORM INDUCED CONSTRAINT VARIATION IN STATIC TIMING ANALYSIS
    3.
    发明申请
    DESIGN RULE CHECKING FOR CONFINING WAVEFORM INDUCED CONSTRAINT VARIATION IN STATIC TIMING ANALYSIS 有权
    设计规则检查波形在静态时间分析中的诱发约束变化

    公开(公告)号：US20150169819A1

    公开(公告)日：2015-06-18

    申请号：US14273724

    申请日：2014-05-09

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Meng-Kai HSU ,  Wen-Hao CHEN

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/5036 ,  G06F2217/84

    摘要： A method for design rule checking (DRC) during static timing analysis (STA) of an integrated circuit (IC) design comprises analyzing cells with distorted waveforms in a cell library and generating both library-based and simulated waveforms for each cell type according to a plurality of parameters for the cell type. The method further comprises constructing a lookup table based on analysis of the distorted waveforms, wherein the lookup table maps waveform error to hold time constraint error of each cell type in the library. The method further comprises identifying one or more cells in the IC design as risky for timing constraint violation during static timing analysis of the IC design according to the lookup table and re-optimizing the identified risky cells to reduce risk for timing violation of the IC design.

    摘要翻译： 在集成电路（IC）设计的静态时序分析（STA）期间的用于设计规则检查（DRC）的方法包括：在单元库中分析具有失真波形的单元，并根据一个单元格类型为每个单元类型产生基于库和模拟波形 用于单元格类型的多个参数。 该方法还包括基于失真波形的分析构建查找表，其中查找表将波形误差映射到库中每个单元类型的保持时间约束误差。 该方法还包括根据查找表在IC设计的静态定时分析期间将IC设计中的一个或多个单元识别为定时约束违反的风险，并重新优化所识别的风险单元以减少IC设计的定时违规风险 。

    COMPRESSION METHOD AND SYSTEM FOR USE WITH MULTI-PATTERNING
    5.
    发明申请
    COMPRESSION METHOD AND SYSTEM FOR USE WITH MULTI-PATTERNING 审中-公开
    使用多种方式的压缩方法和系统

    公开(公告)号：US20140053118A1

    公开(公告)日：2014-02-20

    申请号：US14064229

    申请日：2013-10-28

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Huang-Yu CHEN ,  Chin-Hsiung HSU ,  Wen-Hao CHEN ,  Chung-Hsing WANG

    IPC分类号： G06F17/50

    CPC分类号： G06F17/50 ,  G03F1/70 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： A method comprises (a) providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of an IC by multi-patterning; (b) dividing the plurality of circuit patterns into two or more groups; (c) assigning the circuit patterns within each group to a respective mask to provide mask assignment data, for forming each group of circuit patterns on or in the single layer of the IC; (d) compressing the mask assignment data; and (e) storing the compressed mask assignment data to a non-transitory machine readable storage medium for use by an electronic design automation tool configured for reconstructing the mask assignment data from the compressed data.

    摘要翻译： 一种方法包括（a）提供集成电路（IC）布局，其包括通过多图案化表示要形成在IC的单层上或其中的多个电路图案的数据; （b）将所述多个电路图案分成两组或更多组; （c）将每个组内的电路图案分配给相应的掩模以提供掩模分配数据，以在IC上或其单层中形成每组电路图案; （d）压缩掩模分配数据; 以及（e）将压缩的掩模分配数据存储到非暂时的机器可读存储介质，以供配置用于从压缩数据重建掩模分配数据的电子设计自动化工具使用。

    METHOD AND SYSTEM FOR MULTI-PATTERNING LAYOUT DECOMPOSITION
    6.
    发明申请
    METHOD AND SYSTEM FOR MULTI-PATTERNING LAYOUT DECOMPOSITION 有权
    用于多层布局分解的方法和系统

    公开(公告)号：US20150095857A1

    公开(公告)日：2015-04-02

    申请号：US14043890

    申请日：2013-10-02

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Chin-Hsiung HSU ,  Chin-Chang HSU ,  Yuan-Te HOU ,  Godina HO ,  Wen-Hao CHEN ,  Wen-Ju YANG

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G03F1/00 ,  G03F1/36 ,  G03F1/70 ,  G03F7/70283 ,  G03F7/70466 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. A method for layout decomposition includes determining spacings between adjacent pairs of patterns, and generating a conflict graph having a plurality of sub-graphs, in which a respective vertex corresponds to each respective sub-graph. The patterns within each respective sub-graph are divided into at least a first group and a second group, each of which is assigned to be patterned on the single layer by a respectively different one of a first mask or a second mask. The method further include determining, in a processor, a count of color-rule violations in the plurality of patterns within each respective sub-graph based on a predetermined set of criteria; and within each sub-graph, assigning the first group of patterns in the sub-graph to the one of the first mask or the second mask which results in a smaller count of color-rule violations.

    摘要翻译： 集成电路的单层布局的一部分是多图案化的。 用于布局分解的方法包括确定相邻图案对之间的间隔，以及生成具有多个子图的冲突图，其中相应的顶点对应于每个相应的子图。 每个相应子图中的图案被划分为至少第一组和第二组，其中的每一组被分配为通过第一掩模或第二掩模中的分别不同的一个在单层上被图案化。 该方法还包括在处理器中基于预定的一组标准来确定每个相应子图中的多个模式中的颜色规则违规的计数; 并且在每个子图中，将子图中的第一组图案分配给第一掩码或第二掩码中的一个，导致颜色规则违规的较小数量。

    STATIC TIMING ANALYSIS METHOD AND SYSTEM CONSIDERING CAPACITIVE COUPLING AND DOUBLE PATTERNING MASK MISALIGNMENT
    7.
    发明申请
    STATIC TIMING ANALYSIS METHOD AND SYSTEM CONSIDERING CAPACITIVE COUPLING AND DOUBLE PATTERNING MASK MISALIGNMENT 有权
    静态时序分析方法和系统考虑电容耦合和双模式掩蔽误差

    公开(公告)号：US20140068537A1

    公开(公告)日：2014-03-06

    申请号：US14076330

    申请日：2013-11-11

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Wen-Hao CHEN ,  Yi-Kan CHENG

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/5031 ,  G06F17/504 ,  G06F2217/84

    摘要： A method for analyzing an IC design, comprises: using a computer implemented electronic design automation tool to perform a parasitic RC extraction for a layout of the IC design, the parasitic RC extraction outputting for each of a plurality of routing paths, a nominal capacitive coupling, a minimum capacitive coupling and a maximum capacitive coupling, where the minimum and maximum capacitive couplings correspond to circuit patterning in the presence of double patterning mask misalignments; and performing one of a setup time analysis or a hold time analysis of the IC design using a computer implemented static timing analysis tool. For a given flip-flop having a launch path and a capture path, the setup or hold time analyses is performed using the minimum capacitive coupling for one of the launch and capture paths and the maximum capacitive coupling for the other of the launch and capture paths.

    摘要翻译： 一种用于分析IC设计的方法，包括：使用计算机实现的电子设计自动化工具来执行用于IC设计布局的寄生RC提取，针对多个路由路径中的每一个的寄生RC提取输出，标称电容耦合 最小电容耦合和最大电容耦合，其中最小和最大电容耦合在存在双重图案化掩模未对准的情况下对应于电路图案化; 并使用计算机实现的静态时序分析工具执行IC设计的建立时间分析或保持时间分析之一。 对于具有发射路径和捕获路径的给定触发器，使用用于发射和捕获路径中的一个的最小电容耦合和用于另一个发射和捕获路径的最大电容耦合来执行建立或保持时间分析 。

    METHOD AND SYSTEM FOR REPLACING A PATTERN IN A LAYOUT
    8.
    发明申请
    METHOD AND SYSTEM FOR REPLACING A PATTERN IN A LAYOUT 有权
    用于在布局中替换图案的方法和系统

    公开(公告)号：US20140059504A1

    公开(公告)日：2014-02-27

    申请号：US14068006

    申请日：2013-10-31

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Huang-Yu CHEN ,  Yuan-Te HOU ,  Chung-Min FU ,  Chung-Hsing WANG ,  Wen-Hao CHEN ,  Yi-Kan CHENG

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.

    摘要翻译： 接收到的布局标识要包括在集成电路（IC）层中的多个电路组件，用于使用两个光掩模对层进行双重图案化，所述布局包括要包括在第一光掩模中的多个第一图案和至少一个第二图案 被包括在第二个光掩模中。 所选择的第一模式中的一个具有第一和第二端点，被替换为将第一端点连接到第三端点的替换模式。 除了所选择的第一图案之外，至少一个相应的保留区域被设置为与每个相应的剩余第一图案相邻。 生成表示替换图案的数据，使得在任何保留区域中不形成替换图案的一部分。 输出表示剩余的第一图案和替换图案的数据。

    CELL ROW ARRANGEMENT IN REGIONS OF INTEGRATED CIRCUIT LAYOUT
    10.
    发明申请
    CELL ROW ARRANGEMENT IN REGIONS OF INTEGRATED CIRCUIT LAYOUT 有权

    公开(公告)号：US20210240901A1

    公开(公告)日：2021-08-05

    申请号：US17025296

    申请日：2020-09-18

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Chun-Yao KU ,  Wen-Hao CHEN ,  Ming-Tao YU

    IPC分类号： G06F30/392 ,  G03F1/70

    摘要： A method of generating a layout design of an integrated circuit. The method includes forming a first region having at least two first-type cell rows extending in a first direction. Each one of the first-type cell rows has a first row height measured along a second direction perpendicular to the first direction. The method also includes forming a second region having at least two second-type cell rows extending in the first direction. Each one of the second-type cell rows has a second row height measured along the second direction. The first region is adjacent to the second region, and the first row height of the first-type cell rows is different from the second row height of the second-type cell rows.