公开(公告)号：US20200258846A1

公开(公告)日：2020-08-13

申请号：US16863934

申请日：2020-04-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hui Yu LEE ,  Chin-Chou LIU ,  Cheng-Hung YEH ,  Fong-Yuan CHANG ,  Po-Hsiang HUANG ,  Yi-Kan CHENG ,  Ka Fai CHANG

IPC分类号： H01L23/552 ,  H01L49/02 ,  H01L23/498 ,  H01L23/522 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398

摘要： The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line. The MIM capacitor includes (i) a top capacitor electrode in the first dielectric layer and electrically coupled to the second conducting line; (ii) a bottom capacitor electrode in the first dielectric layer and above the first conducting line, wherein the bottom capacitor electrode is configured to be electrically floating; and (iii) a second dielectric layer between the top and bottom capacitor electrodes.

公开(公告)号：US20150121317A1

公开(公告)日：2015-04-30

申请号：US14277108

申请日：2014-05-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hui Yu LEE ,  Chi-Wen CHANG ,  Chih Ming YANG ,  Ya Yun LIU ,  Yi-Kan CHENG

IPC分类号： G06F17/50

CPC分类号： G03F1/00 ,  G03F1/144 ,  G03F1/70 ,  G03F7/70466 ,  G06F17/5068 ,  G06F17/5081

摘要： A non-transitory, computer readable storage medium is encoded with computer program instructions, such that, when the computer program instructions are executed by a computer, the computer performs a method. The method generates mask assignment information for forming a plurality of patterns on a layer of an integrated circuit (IC) by multipatterning. The mask assignment information includes, for each of the plurality of patterns, a mask assignment identifying which of a plurality of masks is to be used to form that pattern, and a mask assignment lock state for that pattern. User inputs setting the mask assignment of at least one of the plurality of patterns, and its mask assignment lock state are received. A new mask assignment is generated for each of the plurality of patterns having an “unlocked” mask assignment lock state.

摘要翻译： 非暂时的计算机可读存储介质用计算机程序指令编码，使得当计算机程序指令由计算机执行时，计算机执行方法。 该方法通过多图案产生用于在集成电路（IC）的层上形成多个图案的掩模分配信息。 对于多个图案中的每一个，掩模分配信息包括识别多个掩模中哪一个要用于形成该图案的掩模分配以及该图案的掩模分配锁定状态。 用户输入设置多个图案中的至少一个的掩模分配以及其掩码分配锁定状态。 为具有“未锁定”掩码分配锁定状态的多个图案中的每一个生成新的掩模分配。

公开(公告)号：US20220067266A1

公开(公告)日：2022-03-03

申请号：US17523600

申请日：2021-11-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Sheng-Hsiung CHEN ,  Jerry Chang-Jui KAO ,  Fong-Yuan CHANG ,  Po-Hsiang HUANG ,  Shao-Huan WANG ,  XinYong WANG ,  Yi-Kan CHENG ,  Chun-Chen CHEN

IPC分类号： G06F30/398 ,  H01L27/02 ,  G06F30/394

摘要： Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.

公开(公告)号：US20140068537A1

公开(公告)日：2014-03-06

申请号：US14076330

申请日：2013-11-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Hao CHEN ,  Yi-Kan CHENG

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5031 ,  G06F17/504 ,  G06F2217/84

摘要： A method for analyzing an IC design, comprises: using a computer implemented electronic design automation tool to perform a parasitic RC extraction for a layout of the IC design, the parasitic RC extraction outputting for each of a plurality of routing paths, a nominal capacitive coupling, a minimum capacitive coupling and a maximum capacitive coupling, where the minimum and maximum capacitive couplings correspond to circuit patterning in the presence of double patterning mask misalignments; and performing one of a setup time analysis or a hold time analysis of the IC design using a computer implemented static timing analysis tool. For a given flip-flop having a launch path and a capture path, the setup or hold time analyses is performed using the minimum capacitive coupling for one of the launch and capture paths and the maximum capacitive coupling for the other of the launch and capture paths.

摘要翻译： 一种用于分析IC设计的方法，包括：使用计算机实现的电子设计自动化工具来执行用于IC设计布局的寄生RC提取，针对多个路由路径中的每一个的寄生RC提取输出，标称电容耦合 最小电容耦合和最大电容耦合，其中最小和最大电容耦合在存在双重图案化掩模未对准的情况下对应于电路图案化; 并使用计算机实现的静态时序分析工具执行IC设计的建立时间分析或保持时间分析之一。 对于具有发射路径和捕获路径的给定触发器，使用用于发射和捕获路径中的一个的最小电容耦合和用于另一个发射和捕获路径的最大电容耦合来执行建立或保持时间分析 。

公开(公告)号：US20140059504A1

公开(公告)日：2014-02-27

申请号：US14068006

申请日：2013-10-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Huang-Yu CHEN ,  Yuan-Te HOU ,  Chung-Min FU ,  Chung-Hsing WANG ,  Wen-Hao CHEN ,  Yi-Kan CHENG

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.

摘要翻译： 接收到的布局标识要包括在集成电路（IC）层中的多个电路组件，用于使用两个光掩模对层进行双重图案化，所述布局包括要包括在第一光掩模中的多个第一图案和至少一个第二图案 被包括在第二个光掩模中。 所选择的第一模式中的一个具有第一和第二端点，被替换为将第一端点连接到第三端点的替换模式。 除了所选择的第一图案之外，至少一个相应的保留区域被设置为与每个相应的剩余第一图案相邻。 生成表示替换图案的数据，使得在任何保留区域中不形成替换图案的一部分。 输出表示剩余的第一图案和替换图案的数据。

公开(公告)号：US20130239070A1

公开(公告)日：2013-09-12

申请号：US13867154

申请日：2013-04-22

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Cheng-I HUANG ,  Hsiao-Shu CHAO ,  Yi-Kan CHENG

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G03F1/36 ,  G03F1/38 ,  G06F17/5081 ,  G06F2217/84 ,  H01L27/0207

摘要： A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns.

摘要翻译： 一种方法包括使用电子设计自动化工具执行位置和路线操作，以产生用于形成半导体器件的电路图案的光掩模的初步布局。 位置和路线操作受到多个单一图案化间隔物技术（SPST）路由规则约束。 使用RC提取工具在EDA工具内模拟虚拟导电填充图案，以预测要添加到光掩模的初步布局的虚拟导电填充图案的位置和大小。 基于初步布局和仿真虚拟导电填充图案，在EDA工具中执行电路图案的RC定时分析。

公开(公告)号：US20220149033A1

公开(公告)日：2022-05-12

申请号：US17585402

申请日：2022-01-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kam-Tou SIO ,  Jiann-Tyng TZENG ,  Chung-Hsing WANG ,  Yi-Kan CHENG

IPC分类号： H01L27/02 ,  H01L27/092

摘要： An integrated circuit structure includes: an integrated circuit structure includes: a first plurality of cell rows extending in a first direction, and a second plurality of cell rows extending in the first direction. Each of the first plurality of cell rows has a first row height and comprises a plurality of first cells disposed therein. Each of the second plurality of cell rows has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction. The plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction. At least one active region of the first and second pluralities of active regions has a width varying along the first direction.

公开(公告)号：US20150074629A1

公开(公告)日：2015-03-12

申请号：US14542690

申请日：2014-11-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chin-Sheng CHEN ,  Tsun-Yu YANG ,  Wei -Yi HU ,  Tao Wen CHUNG ,  Jui-Feng KUAN ,  Yi-Kan CHENG

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F17/5045

摘要： A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included.

摘要翻译： 一种用于电路设计的方法包括嵌入一个或多个参数化单元的寄生感知库。 寄生感知库用于将表示电路的一些但不是全部寄生效应的网络插入到电路原理图中，使单个电路原理图用于电路仿真，电路的寄生校验和LVS（布局与原理图）检查 。 电路设计过程只需要单一电路原理图，并形成掩模组。 识别单个电路原理图的关键路径，并提取寄生效应并将其插入原理图，使得能够执行寄生验证的预估计，并使用具有一些寄生效应的电路原理图进行LVS检查， 其中包括布局的所有寄生分量的后布局模拟。

公开(公告)号：US20140189623A1

公开(公告)日：2014-07-03

申请号：US13728295

申请日：2012-12-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chin-Sheng CHEN ,  Tsun-Yu YANG ,  Wei-Yi HU ,  Tao Wen CHUNG ,  Jui-Feng KUAN ,  Yi-Kan CHENG

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F17/5045

摘要： A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included.

摘要翻译： 一种用于电路设计的方法包括嵌入一个或多个参数化单元的寄生感知库。 寄生感知库用于将表示电路的一些但不是全部寄生效应的网络插入到电路原理图中，使单个电路原理图用于电路仿真，电路的寄生校验和LVS（布局与原理图）检查 。 电路设计过程只需要单一电路原理图，并形成掩模组。 识别单个电路原理图的关键路径，并提取寄生效应并将其插入原理图，使得能够执行寄生验证的预估计，并使用具有一些寄生效应的电路原理图进行LVS检查， 其中包括布局的所有寄生分量的后布局模拟。

公开(公告)号：US20210257156A1

公开(公告)日：2021-08-19

申请号：US17169118

申请日：2021-02-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ka Fai CHANG ,  Chin-Chou LIU ,  Fong-Yuan CHANG ,  Hui Yu LEE ,  Yi-Kan CHENG

IPC分类号： H01F27/34 ,  H01F27/28 ,  H01F41/04 ,  H01L49/02 ,  H01L23/528 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065 ,  H01L23/48

摘要： An entangled inductor structure generates opposite polarity internal magnetic fields therein to substantially reduce, or cancel, external magnetic fields propagating outside of the entangled inductor structure. These reduced external magnetic fields propagating outside of the entangled inductor structure effectively reduce a keep out zone (KOZ) between the entangled inductor structure and other electrical, mechanical, and/or electro-mechanical components. This allows the entangled inductor structure to be situated closer to these other electrical, mechanical, and/or electro-mechanical components within the IC as compared to conventional inductors which generate larger external magnetic fields.