公开(公告)号：US20200006194A1

公开(公告)日：2020-01-02

申请号：US16433967

申请日：2019-06-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Hsiang HUANG ,  Chin-Chou LIU ,  Chin-Her CHIEN ,  Fong-yuan CHANG ,  Hui Yu LEE

IPC: H01L23/42 ,  H01L25/065 ,  H01L23/367 ,  H01L25/00 ,  H01L23/31

Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.

公开(公告)号：US20210257156A1

公开(公告)日：2021-08-19

申请号：US17169118

申请日：2021-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ka Fai CHANG ,  Chin-Chou LIU ,  Fong-Yuan CHANG ,  Hui Yu LEE ,  Yi-Kan CHENG

IPC: H01F27/34 ,  H01F27/28 ,  H01F41/04 ,  H01L49/02 ,  H01L23/528 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065 ,  H01L23/48

Abstract: An entangled inductor structure generates opposite polarity internal magnetic fields therein to substantially reduce, or cancel, external magnetic fields propagating outside of the entangled inductor structure. These reduced external magnetic fields propagating outside of the entangled inductor structure effectively reduce a keep out zone (KOZ) between the entangled inductor structure and other electrical, mechanical, and/or electro-mechanical components. This allows the entangled inductor structure to be situated closer to these other electrical, mechanical, and/or electro-mechanical components within the IC as compared to conventional inductors which generate larger external magnetic fields.

公开(公告)号：US20210173998A1

公开(公告)日：2021-06-10

申请号：US17179904

申请日：2021-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-yuan CHANG ,  Chin-Chou LIU ,  Chin-Her CHIEN ,  Cheng-Hung YEH ,  Po-Hsiang HUANG ,  Sen-Bor JAN ,  Yi-Kan CHENG ,  Hsiu-Chuan SHU

IPC: G06F30/394 ,  G06F30/392 ,  G06F30/398

Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.

公开(公告)号：US20240312978A1

公开(公告)日：2024-09-19

申请号：US18677345

申请日：2024-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-Yuan CHANG ,  Po-Hsiang HUANG ,  Chin-Chou LIU ,  Chin-Her CHIEN ,  Ka Fai CHANG

IPC: H01L27/02 ,  G11C8/18 ,  H01L23/48 ,  H01L25/065 ,  H01L27/06

CPC classification number: H01L27/0207 ,  G11C8/18 ,  H01L23/481 ,  H01L25/0657 ,  H01L27/0688

Abstract: A layout design methodology is provided for a device that includes two or more identical structures. Each device can have a first die, a second die stacked over the first die and a third die stacked over the second die. The second die can include a first through-silicon via (TSV) and a first circuit, and the third die can include a second TSV and a second circuit. The first TSV and the second TSV can be linearly coextensive. The first and second circuit can each be a logic circuit having a comparator and counter used to generate die identifiers. The counters of respective device die can be connected in series between the dice. Each die can be manufactured using the same masks but retain unique logical identifiers. A given die in a stack of dice can thereby be addressed by a single path in a same die layout.

公开(公告)号：US20230361104A1

公开(公告)日：2023-11-09

申请号：US18224434

申请日：2023-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-Yuan CHANG ,  Po-Hsiang HUANG ,  Chin-Chou LIU ,  Chin-Her CHIEN ,  Ka Fai CHANG

IPC: H01L27/02 ,  H01L27/06 ,  G11C8/18 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L27/0207 ,  H01L27/0688 ,  G11C8/18 ,  H01L23/481 ,  H01L25/0657

Abstract: A layout design methodology is provided for a device that includes two or more identical structures. Each device can have a first die, a second die stacked over the first die and a third die stacked over the second die. The second die can include a first through-silicon via (TSV) and a first circuit, and the third die can include a second TSV and a second circuit. The first TSV and the second TSV can be linearly coextensive. The first and second circuit can each be a logic circuit having a comparator and counter used to generate die identifiers. The counters of respective device die can be connected in series between the dice. Each die can be manufactured using the same masks but retain unique logical identifiers. A given die in a stack of dice can thereby be addressed by a single path in a same die layout.

公开(公告)号：US20210375717A1

公开(公告)日：2021-12-02

申请号：US17403485

申请日：2021-08-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hsiang HUANG ,  Chin-Chou LIU ,  Chin-Her CHIEN ,  Fong-yuan CHANG ,  Hui Yu LEE

IPC: H01L23/42 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/367

Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.

公开(公告)号：US20200258846A1

公开(公告)日：2020-08-13

申请号：US16863934

申请日：2020-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui Yu LEE ,  Chin-Chou LIU ,  Cheng-Hung YEH ,  Fong-Yuan CHANG ,  Po-Hsiang HUANG ,  Yi-Kan CHENG ,  Ka Fai CHANG

IPC: H01L23/552 ,  H01L49/02 ,  H01L23/498 ,  H01L23/522 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line. The MIM capacitor includes (i) a top capacitor electrode in the first dielectric layer and electrically coupled to the second conducting line; (ii) a bottom capacitor electrode in the first dielectric layer and above the first conducting line, wherein the bottom capacitor electrode is configured to be electrically floating; and (iii) a second dielectric layer between the top and bottom capacitor electrodes.

公开(公告)号：US20200020635A1

公开(公告)日：2020-01-16

申请号：US16507629

申请日：2019-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-Yuan CHANG ,  Chin-Chou LIU ,  Chin-Her CHIEN ,  Po-Hsiang HUANG ,  Noor Mohamed ETTUVEETTIL

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/532

Abstract: The present disclosure describes a semiconductor structure includes a first chip with a first conductive line and a first conductive island formed on the first conductive line. The first chip also includes a first plurality of vias formed in the first conductive island and electrically coupled to the first conductive line. The semiconductor structure further includes a second chip bonded to the first chip, where the second chip includes a second conductive line and a second conductive island formed on the second conductive line. The second chip also includes a second plurality of vias formed in the second conductive island and electrically coupled to the second conductive line.

公开(公告)号：US20230205967A1

公开(公告)日：2023-06-29

申请号：US18171072

申请日：2023-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-yuan CHANG ,  Chin-Chou LIU ,  Chin-Her CHIEN ,  Cheng-Hung YEH ,  Po-Hsiang HUANG ,  Sen-Bor JAN ,  Yi-Kan CHENG ,  Hsiu-Chuan SHU

IPC: G06F30/394 ,  G06F30/392 ,  G06F30/398

CPC classification number: G06F30/394 ,  G06F30/392 ,  G06F30/398

Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.

公开(公告)号：US20170169154A1

公开(公告)日：2017-06-15

申请号：US14967061

申请日：2015-12-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Hung LIN ,  Chung-Hsing WANG ,  Chin-Chou LIU ,  Chi-Wei HU

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5081 ,  G06F17/509

Abstract: A method is disclosed that includes the operation below. Vertices in a conflict graph are sorted into a first clique and a second clique, in which the conflict graph corresponds to a layout of a circuit. A first vertex of the vertices is merged with a second vertex of the vertices, to generate a reduced graph, in which the first clique excludes the second vertex, and the second clique excludes the first vertex. A first color pattern of a plurality of color patterns is assigned to a first pattern, corresponding to the first vertex, and a second pattern, corresponding to the second vertex, in the layout according to the reduced graph.