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公开(公告)号：US20180357351A1
公开(公告)日：2018-12-13
申请号：US15882288
申请日：2018-01-29
发明人： Yen-Hung LIN , Chung-Hsing WANG , Yuan-Te HOU
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/02
摘要： The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes partitioning a layout area into one or more contiguous units, where each unit includes a plurality of placement sites. The method also includes mapping a first set of pin locations and a second set of pin locations to each of the one or more contiguous units. The method further includes placing a cell in the one or more contiguous units, where the cell is retrieved from a cell library that includes a plurality of pin locations for the cell. The placement of the cell is based on an allocation of one or more pins associated with the cell to at least one of a pin track from the first plurality of pin locations, a pin track from second plurality of pin locations, or a combination thereof.
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公开(公告)号：US20240086610A1
公开(公告)日：2024-03-14
申请号：US18513349
申请日：2023-11-17
发明人： Yen-Hung LIN , Yuan-Te HOU , Chung-Hsing WANG
IPC分类号： G06F30/392 , G06F30/39
CPC分类号： G06F30/392 , G06F30/39 , G06F30/398
摘要： A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.
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公开(公告)号：US20180165406A1
公开(公告)日：2018-06-14
申请号：US15595863
申请日：2017-05-15
发明人： Yen-Hung LIN , Yuan-Te HOU , Chin-Chang HSU
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/70 , G06F2217/12
摘要： A method includes operations below. A layout of a circuit is converted to a first conflict graph. A first vertex and a second vertex in the first conflict graph are adjusted based on first data indicating a color patterns assignment for the circuit, in order to generate a second conflict graph, in which the first vertex indicates a first pattern in the layout, and the second vertex indicates a second pattern in the layout. According to the second conflict graph, a first color pattern is assigned to both of the first pattern and the second pattern, or the first color pattern is assigned to the first pattern and a second color pattern is assigned to the second pattern, in order to generate second data for fabricating the circuit.
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公开(公告)号：US20180210993A1
公开(公告)日：2018-07-26
申请号：US15723308
申请日：2017-10-03
发明人： Yen-Hung LIN , Yuan-Te HOU , Chung-Hsing WANG
IPC分类号： G06F17/50
摘要： A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes forming a first partition by selecting at least one in-boundary PG cell from the group of PG cells, adding at least one out-boundary PG cell from the group of PG cells into the first partition, forming a second partition by selecting the remaining in-boundary PG cells and the remaining out-boundary PG cells in the group of PG cells, calculating the total area of the in-boundary PG cells in the first partition, calculating the total area of the out-boundary PG cells in the first partition, calculating the total area of the in-boundary PG cells in the second partition, calculating the total area of the out-boundary PG cells in the second partition, and calculating the difference between the total areas of in-boundary PG cells in the first partition and the out-boundary PG cells in the first partition.
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公开(公告)号：US20170169154A1
公开(公告)日：2017-06-15
申请号：US14967061
申请日：2015-12-11
发明人： Yen-Hung LIN , Chung-Hsing WANG , Chin-Chou LIU , Chi-Wei HU
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5081 , G06F17/509
摘要： A method is disclosed that includes the operation below. Vertices in a conflict graph are sorted into a first clique and a second clique, in which the conflict graph corresponds to a layout of a circuit. A first vertex of the vertices is merged with a second vertex of the vertices, to generate a reduced graph, in which the first clique excludes the second vertex, and the second clique excludes the first vertex. A first color pattern of a plurality of color patterns is assigned to a first pattern, corresponding to the first vertex, and a second pattern, corresponding to the second vertex, in the layout according to the reduced graph.
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6.发明申请EDA TOOL AND METHOD FOR CONFLICT DETECTION DURING MULTI-PATTERNING LITHOGRAPHY 审中-公开EDA工具和多层次图像冲突检测方法公开(公告)号：US20150363541A1
公开(公告)日：2015-12-17
申请号：US14833364
申请日：2015-08-24
发明人： Yen-Hung LIN , Cheng-I HUANG , Chin-Chang HSU , Hung Lung LIN
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/06
摘要： A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing.
摘要翻译： 一种方法包括访问表示具有多个多边形的集成电路（IC）的层的布局的数据，该多个多边形定义要在半导体衬底的单个层上的数个（N个）光掩模中划分的电路图案，其中N较大 比两个。 该方法还包括输入具有多个顶点的冲突图，识别第一和第二顶点，每个顶点连接到第三和第四顶点，其中第三和第四顶点连接到冲突图的相同边缘;以及 合并第一和第二顶点以形成缩小图。 所述方法还包括检测所述缩小的至少一个或多个顶点具有冲突。 在一个方面，该方法通过执行图案移位，针迹插入或重新路由之一来解决检测到的冲突。
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公开(公告)号：US20210326509A1
公开(公告)日：2021-10-21
申请号：US17363669
申请日：2021-06-30
发明人： Yen-Hung LIN , Yuan-Te Hou , Chung-Hsing Wang
IPC分类号： G06F30/392 , G06F30/39
摘要： A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.
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公开(公告)号：US20200226316A1
公开(公告)日：2020-07-16
申请号：US16837449
申请日：2020-04-01
发明人： Yen-Hung LIN , Chung-Hsing Wang , Yuan-Te Hou
IPC分类号： G06F30/392
摘要： The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes partitioning a layout area into one or more contiguous units, where each unit includes a plurality of placement sites. The method also includes mapping a first set of pin locations and a second set of pin locations to each of the one or more contiguous units. The method further includes placing a cell in the one or more contiguous units, where the cell is retrieved from a cell library that includes a plurality of pin locations for the cell. The placement of the cell is based on an allocation of one or more pins associated with the cell to at least one of a pin track from the first plurality of pin locations, a pin track from second plurality of pin locations, or a combination thereof.
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公开(公告)号：US20190033707A1
公开(公告)日：2019-01-31
申请号：US15882235
申请日：2018-01-29
发明人： Hsing-Lin YANG , Chin-Chang HSU , Yen-Hung LIN , Chung-Hsing WANG , Wen-Ju YANG
摘要： A method for mitigating extreme ultraviolet (EUV) mask defects is disclosed. The method includes the steps of providing a wafer blank, identifying a first plurality of defects on the wafer blank, providing an EUV mask design on top of the wafer blank, identifying non-critical blocks with corresponding stretchable zones on the EUV mask design, overlapping the EUV blank with the EUV mask design, identifying a second plurality of defects, the second plurality of defects are solved, identifying a third plurality of defects, the third plurality of defects are not solved, adjusting the relative locations of the EUV mask design and the EUV blank to solve at least one of the third plurality of defects, and adjusting the locations of at least one of the non-critical blocks within corresponding stretchable zones to solve at least one of the third plurality of defects.
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