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1.发明申请EDA TOOL AND METHOD FOR CONFLICT DETECTION DURING MULTI-PATTERNING LITHOGRAPHY 审中-公开EDA工具和多层次图像冲突检测方法公开(公告)号：US20150363541A1
公开(公告)日：2015-12-17
申请号：US14833364
申请日：2015-08-24
发明人： Yen-Hung LIN , Cheng-I HUANG , Chin-Chang HSU , Hung Lung LIN
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/06
摘要： A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing.
摘要翻译： 一种方法包括访问表示具有多个多边形的集成电路（IC）的层的布局的数据，该多个多边形定义要在半导体衬底的单个层上的数个（N个）光掩模中划分的电路图案，其中N较大 比两个。 该方法还包括输入具有多个顶点的冲突图，识别第一和第二顶点，每个顶点连接到第三和第四顶点，其中第三和第四顶点连接到冲突图的相同边缘;以及 合并第一和第二顶点以形成缩小图。 所述方法还包括检测所述缩小的至少一个或多个顶点具有冲突。 在一个方面，该方法通过执行图案移位，针迹插入或重新路由之一来解决检测到的冲突。
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公开(公告)号：US20130254726A1
公开(公告)日：2013-09-26
申请号：US13902102
申请日：2013-05-24
发明人： Chin-Chang HSU , Ying-Yu SHEN , Wen-Ju YANG , Hsiao-Shu CHAO , Yi-Kan CHENG
IPC分类号： G06F17/50
摘要： A method includes receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool. The layout includes a plurality of polygons to be formed in the DPT-layer by a multi-patterning process. First and second ones of the plurality of polygons to be formed using first and second photomasks, respectively are identified. Any intervening polygons along a first path connecting the first polygon to the second polygon, and separator regions between adjacent polygons along the first path are identified. The separator regions have sizes less than a minimum threshold distance between polygons formed on the first photomask. The separator regions are counted. A multi-patterning conflict is identified, if the count of separator regions is even, prior to assigning all remaining ones of the plurality of polygons to the first or second masks.
摘要翻译： 一种方法包括接收表示由位置和路线工具生成的集成电路的DPT层的布局的数据。 该布局包括通过多图案化工艺在DPT层中形成的多个多边形。 分别使用第一和第二光掩模形成的多个多边形中的第一和第二多边形。 识别沿着连接第一多边形到第二多边形的第一路径以及沿着第一路径的相邻多边形之间的分隔区域的任何中间多边形。 分离器区域具有小于形成在第一光掩模上的多边形之间的最小阈值距离的尺寸。 计数分离器区域。 在将所述多个多边形中的所有剩余的多边形分配给第一或第二掩模之前，如果分离器区域的计数是偶数，则识别多图案化冲突。
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公开(公告)号：US20180165406A1
公开(公告)日：2018-06-14
申请号：US15595863
申请日：2017-05-15
发明人： Yen-Hung LIN , Yuan-Te HOU , Chin-Chang HSU
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/70 , G06F2217/12
摘要： A method includes operations below. A layout of a circuit is converted to a first conflict graph. A first vertex and a second vertex in the first conflict graph are adjusted based on first data indicating a color patterns assignment for the circuit, in order to generate a second conflict graph, in which the first vertex indicates a first pattern in the layout, and the second vertex indicates a second pattern in the layout. According to the second conflict graph, a first color pattern is assigned to both of the first pattern and the second pattern, or the first color pattern is assigned to the first pattern and a second color pattern is assigned to the second pattern, in order to generate second data for fabricating the circuit.
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公开(公告)号：US20200167519A1
公开(公告)日：2020-05-28
申请号：US16587700
申请日：2019-09-30
IPC分类号： G06F30/398 , G03F1/36
摘要： A method of generating a plurality of photomasks includes generating a circuit graph. The circuit graph comprises a plurality of vertices and a plurality of edges. Each of the plurality of vertices is representative of one of a plurality of conductive lines. The plurality of edges are representative of a spacing between the conductive lines less than an acceptable minimum distance. Kn+1 graph comprising a first set of vertices selected from the plurality of vertices connected in series by a first set of edges selected from the plurality of edges and having at least one non-series edge connection between a first vertex and a second vertex selected from the first set of vertices is reduced by merging a third vertex into a fourth vertex selected from the first set of the plurality of vertices. An n-pattern conflict check is performed and the photomasks generated based on the result.
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公开(公告)号：US20150095857A1
公开(公告)日：2015-04-02
申请号：US14043890
申请日：2013-10-02
发明人： Chin-Hsiung HSU , Chin-Chang HSU , Yuan-Te HOU , Godina HO , Wen-Hao CHEN , Wen-Ju YANG
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/00 , G03F1/36 , G03F1/70 , G03F7/70283 , G03F7/70466 , G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. A method for layout decomposition includes determining spacings between adjacent pairs of patterns, and generating a conflict graph having a plurality of sub-graphs, in which a respective vertex corresponds to each respective sub-graph. The patterns within each respective sub-graph are divided into at least a first group and a second group, each of which is assigned to be patterned on the single layer by a respectively different one of a first mask or a second mask. The method further include determining, in a processor, a count of color-rule violations in the plurality of patterns within each respective sub-graph based on a predetermined set of criteria; and within each sub-graph, assigning the first group of patterns in the sub-graph to the one of the first mask or the second mask which results in a smaller count of color-rule violations.
摘要翻译： 集成电路的单层布局的一部分是多图案化的。 用于布局分解的方法包括确定相邻图案对之间的间隔，以及生成具有多个子图的冲突图，其中相应的顶点对应于每个相应的子图。 每个相应子图中的图案被划分为至少第一组和第二组，其中的每一组被分配为通过第一掩模或第二掩模中的分别不同的一个在单层上被图案化。 该方法还包括在处理器中基于预定的一组标准来确定每个相应子图中的多个模式中的颜色规则违规的计数; 并且在每个子图中，将子图中的第一组图案分配给第一掩码或第二掩码中的一个，导致颜色规则违规的较小数量。
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公开(公告)号：US20140223391A1
公开(公告)日：2014-08-07
申请号：US14251696
申请日：2014-04-14
发明人： Chung-Min FU , Yung-Fong LU , Wen-Ju YANG , Chin-Chang HSU
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/70
摘要： Apparatus includes a machine readable storage medium for storing a template library having at least one template. The template is to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC. The pattern has a plurality of portions to be formed using a plurality of respectively different photomasks. The first layout representation includes data identifying on which photomask each portion is to be located. An electronic design automation (EDA) tool includes a processor configured to receive a hardware description language representation of at least a part of a circuit and generate a second layout representation of the part of the circuit having a plurality of polygons. The EDA tool has a matching module that identifies and outputs an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons.
摘要翻译： 装置包括用于存储具有至少一个模板的模板库的机器可读存储介质。 该模板将包括通过多图案化IC的单层而形成的至少一个图案的第一布局图示。 该图案具有使用多个分别不同的光掩模形成的多个部分。 第一布局表示包括识别每个部分将要位于哪个光掩模上的数据。 电子设计自动化（EDA）工具包括被配置为接收电路的至少一部分的硬件描述语言表示并且生成具有多个多边形的电路的一部分的第二布局表示的处理器。 EDA工具具有匹配模块，其识别并输出多个部分中的一个或多个部分是否匹配多个多边形的子集的指示。
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公开(公告)号：US20210279398A1
公开(公告)日：2021-09-09
申请号：US17327343
申请日：2021-05-21
IPC分类号： G06F30/398 , G03F1/36
摘要： A method of generating a plurality of photomasks includes generating a circuit graph. The circuit graph comprises a plurality of vertices and a plurality of edges. Each of the plurality of vertices is representative of one of a plurality of conductive lines. The plurality of edges are representative of a spacing between the conductive lines less than an acceptable minimum distance. Kn+1 graph comprising a first set of vertices selected from the plurality of vertices connected in series by a first set of edges selected from the plurality of edges and having at least one non-series edge connection between a first vertex and a second vertex selected from the first set of vertices is reduced by merging a third vertex into a fourth vertex selected from the first set of the plurality of vertices. An n-pattern conflict check is performed and the photomasks generated based on the result.
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公开(公告)号：US20190033707A1
公开(公告)日：2019-01-31
申请号：US15882235
申请日：2018-01-29
发明人： Hsing-Lin YANG , Chin-Chang HSU , Yen-Hung LIN , Chung-Hsing WANG , Wen-Ju YANG
摘要： A method for mitigating extreme ultraviolet (EUV) mask defects is disclosed. The method includes the steps of providing a wafer blank, identifying a first plurality of defects on the wafer blank, providing an EUV mask design on top of the wafer blank, identifying non-critical blocks with corresponding stretchable zones on the EUV mask design, overlapping the EUV blank with the EUV mask design, identifying a second plurality of defects, the second plurality of defects are solved, identifying a third plurality of defects, the third plurality of defects are not solved, adjusting the relative locations of the EUV mask design and the EUV blank to solve at least one of the third plurality of defects, and adjusting the locations of at least one of the non-critical blocks within corresponding stretchable zones to solve at least one of the third plurality of defects.
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公开(公告)号：US20180068049A1
公开(公告)日：2018-03-08
申请号：US15255489
申请日：2016-09-02
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G06F2217/12 , Y02P90/265
摘要： A method of generating a plurality of photomasks includes generating a circuit graph. The circuit graph comprises a plurality of vertices and a plurality of edges. Each of the plurality of vertices is representative of one of a plurality of conductive lines. The plurality of edges are representative of a spacing between the conductive lines less than an acceptable minimum distance. Kn+1 graph comprising a first set of vertices selected from the plurality of vertices connected in series by a first set of edges selected from the plurality of edges and having at least one non-series edge connection between a first vertex and a second vertex selected from the first set of vertices is reduced by merging a third vertex into a fourth vertex selected from the first set of the plurality of vertices. An n-pattern conflict check is performed and the photomasks generated based on the result.
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公开(公告)号：US20150379189A1
公开(公告)日：2015-12-31
申请号：US14819590
申请日：2015-08-06
发明人： Hung Lung LIN , Chin-Chang HSU , Min-Yuan TSAI , Wen-Ju YANG , Chien Lin HO
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F7/0035 , G06F17/509
摘要： Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium.
摘要翻译： 提供了一种用于在半导体制造中评估和分解用于三重图案光刻的半导体器件电平的方法。 该方法包括使用各种方法生成冲突图并简化冲突图，以产生可以进一步简化或评估分解有效性的简化冲突图。 本公开还提供将分解有效性规则应用于简化的冲突图，以确定冲突图是否表示可分解成三个掩模的半导体器件层。 公开的方法由计算机执行，并且用于执行该方法的指令可以存储在计算机可读存储介质上。
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