公开(公告)号：US20150363541A1

公开(公告)日：2015-12-17

申请号：US14833364

申请日：2015-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung LIN ,  Cheng-I HUANG ,  Chin-Chang HSU ,  Hung Lung LIN

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/06

Abstract: A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing.

Abstract translation: 一种方法包括访问表示具有多个多边形的集成电路（IC）的层的布局的数据，该多个多边形定义要在半导体衬底的单个层上的数个（N个）光掩模中划分的电路图案，其中N较大 比两个。 该方法还包括输入具有多个顶点的冲突图，识别第一和第二顶点，每个顶点连接到第三和第四顶点，其中第三和第四顶点连接到冲突图的相同边缘;以及 合并第一和第二顶点以形成缩小图。 所述方法还包括检测所述缩小的至少一个或多个顶点具有冲突。 在一个方面，该方法通过执行图案移位，针迹插入或重新路由之一来解决检测到的冲突。

公开(公告)号：US20150379189A1

公开(公告)日：2015-12-31

申请号：US14819590

申请日：2015-08-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung Lung LIN ,  Chin-Chang HSU ,  Min-Yuan TSAI ,  Wen-Ju YANG ,  Chien Lin HO

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F7/0035 ,  G06F17/509

Abstract: Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium.

Abstract translation: 提供了一种用于在半导体制造中评估和分解用于三重图案光刻的半导体器件电平的方法。 该方法包括使用各种方法生成冲突图并简化冲突图，以产生可以进一步简化或评估分解有效性的简化冲突图。 本公开还提供将分解有效性规则应用于简化的冲突图，以确定冲突图是否表示可分解成三个掩模的半导体器件层。 公开的方法由计算机执行，并且用于执行该方法的指令可以存储在计算机可读存储介质上。

公开(公告)号：US20140372958A1

公开(公告)日：2014-12-18

申请号：US14302684

申请日：2014-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung Lung LIN ,  Chin-Chang HSU ,  Min-Yuan TSAI ,  Wen-Ju YANG ,  Chien Lin HO

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F7/0035 ,  G06F17/509

Abstract: Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium.

Abstract translation: 提供了一种用于在半导体制造中评估和分解用于三重图案光刻的半导体器件电平的方法。 该方法包括使用各种方法生成冲突图并简化冲突图，以产生可以进一步简化或评估分解有效性的简化冲突图。 本公开还提供将分解有效性规则应用于简化的冲突图，以确定冲突图是否表示可分解成三个掩模的半导体器件层。 公开的方法由计算机执行，并且用于执行该方法的指令可以存储在计算机可读存储介质上。